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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M30222 single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high-level of instruction efficiency and are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M30222 group includes a range of products with various package types.
Features
* Memory capacity ......................................... Flash ROM 260 Kbytes ...................................................................... RAM 20 Kbytes * Shortest instruction execution time ............. 62.5ns (f(XIN)=16MHZ) * Supply voltage ............................................ 2.7 to 5.5V * Low power consumption ............................. TBD * Interrupts ..................................................... 25 internal and 8 external interrupt sources 4 software interrupt sources 7 levels (including key input interrupt) * Multifunction 16-bit timer ............................. 5 output timers, 6 input timers, three phase motor control, real-time port * Serial I/O ..................................................... 5 channel 3 for UART or clock synchronous (1 channel for I2C or SPI) 2 for clock synchronous * DMAC ........................................................... 2 channels (trigger: 24 sources) * A-D converter ............................................... 10 bits X 8 channels (expandable up to 10 channels) * D-A converter ............................................... 8 bits X 2 channels * CRC calculation circuit ................................. 1 circuit * Watchdog timer ............................................ 1 timer * Key-on Wake up ........................................... 8 inputs * Programmable I/O ........................................ 54 lines * Input port ...................................................... 1 line (P83 shared with NMI pin) * Clock generating circuit ............................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) *LCD Drive ...................................................... 1/2, 1/3 bias 4 common outputs 40 segment outputs Built-in charge pump 1/2, 1/3, 1/4 duty Expansion CLK output Static/direct drive mode
Specifications written in this manual are believed to be accurate but are not guaranteed to be entirely error free. They may be changed for functional or performance improvements. Please make sure your manual is the latest version.
Applications
Audio, cameras, office, industrial, communications and, portable equipment
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r de n t Un p m e o l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table of Contents
Description ............................................................ 1-2 Operation of Functional Blocks ............................ 1-10 Memory ............................................................... 1-10 Central Processing Unit (CPU) ............................ 1-11 Reset ................................................................... 1-14 Special function registers ..................................... 1-15 Software Reset .................................................... 1-20 Clock generating Circuit ...................................... 1-21 Clock Output ........................................................ 1-25 Wait Mode ........................................................... 1-26 Stop Mode ........................................................... 1-27 Status Transition Of BCLK ................................... 1-28 Voltage Down Converter ...................................... 1-30 Power control....................................................... 1-32 Protection ............................................................ 1-34 Software wait ....................................................... 1-35 Overview of Interrupts .......................................... 1-36 Watchdog Timer .................................................. 1-57 DMAC .................................................................. 1-59 Timers ................................................................. 1-69 Timer A ................................................................ 1-71 Timer B ................................................................ 1-85 Timer functions for three-phase motor control ..... 1-93 Serial Communications ...................................... 1-105 (1) Clock synchronous serial I/O mode .............. 1-114 (2) Clock Asynchronous Serial I/O (UART) Mode1-120 UART2 in I2C Mode .......................................... 1-130 UART2 in SPI mode .......................................... 1-138 S I/O 3, 4 ........................................................... 1-143 LCD Drive Control Circuit .................................. 1-147 A-D Converter ................................................... 1-157 D-A Converter .................................................... 1-168 CRC Calculation Circuit ..................................... 1-170 Programmable I/O Ports .................................... 1-172 Electrical Characteristics ................................... 1-179 Flash Memory .................................................... 1-186 CPU Rewrite Mode ............................................ 1-188 Parallel I/O Mode ............................................... 1-202 Standard serial I/O mode 1 ................................ 1-206 Standard serial I/O mode 2 ................................ 1-226
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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figure 1.1 shows the pin configurations for M30222 group.
P97/ADtrg/LED7/Sin4/INT3 100
P106/AN6/INT6
P107/AN7/INT7
P100/AN0
P103/AN3
P102/AN2
P104/AN4
P105/AN5
P101/AN1
COM2
COM0
COM1
AVcc 99
AVss
Vref 98
VL2
VL1
VL3
C2
C1
92
97
96
95
94
93
91
90
89
88
87
86
85
84
83
82
81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P96/ANEX1/Sout4 P95/ANEX0/CLK4 P94/DA1/TB4in P93/DA0/TB3in P92/TB2in/Sout3 P91/TB1in/Sin3 P90/TB0in/INT2/CLK3 P86/INT1 CNVss P85/Xcin P84/Xcout RESET Xout Vss Xin Vcc P83/NMI P82/INT0 P81/TA4IN/INT5/U P80/TA4OUT/INT5/U P77/TA3IN/INT4 P76/TA3OUT/INT4 P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TxD2/SDA/TA0OUT P67/TxD1/KI7 P66/RxD1/KI6
COM3 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 SEG14 Vss SEG15 VDC Vcc SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P30 SEG25/P31
Fig. 1.1. Pin configuration (top view)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 35 31 P65/CLK1/KI5 32 P64/CTS1/RTS1/CTS0/CLKS1/KI4 P63/TxD0/KI3 P61/CLK0/KI1 P62/RxD0/KI2
M30222FG
43
45
42
44
36 P60/CTS0/RTS0/KI0
37 SEG39/P47/RTP1
38 SEG38/P46/RTP0
40 SEG36/P44
46
48
49
47
41
50
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39 SEG37/P45
SEG35/P43
SEG33/P41
SEG31/P37
SEG30/P36
SEG29/P35
SEG34/P42
SEG32/P40
SEG28/P34
SEG27/P33
SEG26/P32
r de n t Un p m e o l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.2 is a block diagram of the M30222 group.
4 24 8 8 8
I/O ports
Internal peripheral functions
Timer
COM 0-3
SEG 0-23
Port P3 SEG 24-31
Port P4 SEG 32-39
Port P6
Port P7
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) Watchdog timer
(15 bits)
System clock generator XIN-XOUT XCIN-XCOUT
Clock synchronous SI/O
8
Port P8
UART/clock synchronous SI/O
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT ) 5 (Polynomial :X16 +X12 +X +1)
(8 bits X 2 channels)
LCD Controller VDC
6
Port P83
M16C/60 series16-bit CPU core
Registers R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB SB Program counter PC Vector table INTB Stack pointer ISP USP FLG
Memory
ROM (Note 1)
1
Port P9
RAM (Note 2)
DMAC
(2 channels)
8
Port P10
D-A converter
(8 bits X 2 channels)
Multiplier
8
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
Fig. 1.2. Block diagram of M30222 group
Memory Expansion
Figure 1.3 shows the Memory expansion for the M30222 group.
ROM size (Bytes) 260K 128K 96K 64K 32K 20K SRAM Flash Memory Version M30222FC/FP/GP
Fig. 1.3. Memory Expansion
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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1. Performance outline of the M30222 group
Parameters Number of basic instructions Shortest instruction execution time ROM Memory size RAM P3-P4, P6-P10 except P83 P83 Multifunctional timer Serial I/O I/O I 91 62.5ns f(Xin) = 16MHz 260K bytes 20K bytes 8 bits x 6, 7 bits x 1 1 bit x 1 16 bits x 5
Functions
Input/Output
TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2, TB3, TB4, TB5 UART0, UART1, UART2 SIO3, SIO4
16 bits x 6, three-phase motor control (UART or clock synchronous) x 3, or I2C x 1 (Clock synchronous) x 2 10 bits x (8 + 2) channels 8 bits x 2 CRC-CCITT 15 bits x 1 (with prescaler) 25 external, 8 internal sources, 4 software, 7 levels 2 built-in clock generation circuits 2.7 to 5.5V f(Xin) = 16 MHz, without software wait TBD
A-D converter D-A converter CRC calculation circuit Watchdog timer Interrupts Clock generating circuit Supply voltage Power consumption I/O characteristics I/O withstand voltage P3, P4 Output current Device configuration Package COM0 to COM3 LCD SEG0 to SEG39 P6-P10
5.5V 0.1 mA (high output), 2.5 mA (low output) 5 mA at 5V (excluding pins P70, P71, P83) CMOS high performance silicon gate 100-pin plastic mold QFP 4 lines 40 lines (16 lines shared with I/O ports)
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r de n t Un p m e o l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M30222 group: (1) Support for Flash memory version and mask ROM versions (2) ROM capacity: 260 K bytes (3) Package 100P6S-A : Plastic molded QFP (mask ROM version) 100P6Q-A: Plastic molded QFP
M16C Family Group
Figure 1.4 shows the M30222 family.
Type No. M30222 F G - XXX FP Package type: FP: Package GP: 100P6S-A 100P6Q-A
ROM No. Omitted for flash memory version ROM capacity: G: 260K bytes Memory type: F : Flash memory version M30222 Group M16C Family
Fig. 1.4. Type No., memory size, and package
Table 1.2 shows the product list for the M30222 family.
Table 1.2. Product list
Type No. M30222FGFP M30222FGGP 260 Kbytes 20 Kbytes ROM Capacity RAM Capacity Package Type 100P6S-A Flash 100P6Q-A Remarks
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MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Table 1.3. Pin Description for M30222 group
Pin name Vcc, Vss VDC Signal name Power supply Voltage Down Converter CNVss Reset input Main Clock Input Input/Output I/O type Input Input Function Supply 2.7 to 5.5V to the Vcc pin and 0V to Vss Connects capacitor from VDC to Vss; or if not using VDC, connect 3.3V to VDC pin.
CNVss RESET Xin, Xout
This pin is used to enable flash programming. Connect the pull-down resistor from CNVss to Vss. Connect CNVss to enable flash programming. An "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the Xin and the Xout pins. To use an externally derived clock, input it to the Xin. These pins are provided for the subclock generating circuit. Connect a ceramic resonator or crystal between the Xcin pin and leave the Xcout pin open. These pins also function as CMOS I/O ports. This pin is a power supply input for the A-D converter. Connect this pin to Vcc. This pin is a power supply input for A-D converter. Connect this pin to Vss.
P84/P85 Xcout/Xcin AVcc
I/O Port Subclock Analog power supply + reference Analog power supply + reference Reference voltage input I/O Port P3
Input/Output Input/Output Input Input
AVss
Vref
Input
This pin is a reference voltage input for the A-D converter.
Input/Output Output Output Input/Output Output Output Input/Output Input Input/Output
P30 to P37
RTP0_0 to RTP3_1 SEG24 to SEG31 I/O Port P4
This is an 8-bit CMOS I/O port. It has an input/output direction register that allows the user to set each pin for input or output individually. When used for input, the port can be set by software to have or not have a pull resistor in units of four bits. Pins in this port also function as SEG output for LCD and output for Real-time port. This is an 8-bit I/O port equivalent to P3. Pins in Port 4 also function as SEG outputs for LCD. Pins in Port 4 also function as Real-time port. This is an 8-bit I/O port equivalent to P3. Pins in Port 6 also function as key-input interrupts. Pins in Port 6 also function as transmit, receive, clock, and CTS/RTS pins for UART0, UART1. This is an 8-bit I/O port equivalent to P3. Some pins in Port 7 serve as transmit, receive, clock, and CTS/RTS for UART2. UART2 provides I2C serial communications. Some pins in Port 7 serve as input/output for Timer A and Timer B. Pins P76 and P77 function as inputs for INT4. Some pins in Port 7 function as three-phase outputs for V, V, W, and W. P80 to P82, P86 are I/O ports equivalent to P3. Some pins in Port 8 serve as input/output for Timer A and Timer B. Pins P80 and P81 function as inputs for INT5. Pins P80 and P81 function as inputs three-phase outputs for U and U. P83 is an input only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from "H" to "L". The NMI function cannot be cancelled using software. The pull-up resistor cannot be set for this pin.
P40 to P47
SEG32 to SEG39 RTP4_0 to RTP7_1 I/O Port P6 KI0 to KI7
P60 to P67 UART0, UART1
I/O Port P7 UART2 P70 to P77 Timer A/B INT4 Three-phase I/O Port P8 Timer A INT5 Three-phase
Input/Output Input/Output
Input/Output Input Output Input/Output Input/Output Input Output
P80 to P82, P86
P83
NMI
Input
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r de n t Un p m e o l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Description
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin name
Signal name I/O Port P9 SIO 3/4 Timer B
I/O type Input/Output Input/Output Input Output Input Output This is an 8-bit I/O equivalent to P3.
Function
Pins in Port 9 function as transmit, receive and clock for SIO3 and SIO4. Some pins in Port 9 serve as TB3 and TB4 pins. P93 and P94 can be configured to function as a digital to analog output. Pin P90 and P97 can be configured as INT2 and INT3.
P90 to P97
D-A INT2, INT3 ANEX0 ANEX1 I/O Port 10
These pins are used to connect to an optional external op amp. Input Input/Output Input Input This is an 8-bit I/O port equivalent to P3. Pins in Port 10 function as analog inputs. P106 and P107 function as inputs for INT6 and INT7. Pins in this port function as SEG output for LCD drive circuit. Pins in this port function as COM output for LCD drive circuit. Power supply input for LCD drive circuit.
P100 to P107
AN0 to AN7 INT6, INT7
SEG0 to SEG23 COM0 to COM3 VL1 to VL3
SEG drive pins COM ports Power supply for LCD driver
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MITSUBISHI MICROCOMPUTERS
Rev. G Memory
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M30222 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, LCD, and I/O ports. The following explains each unit.
Memory
Figure 1.5 is a memory map of the M30222 group. The linear address space of 1M bytes extends from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30222FG-XXXFP, there is 256K bytes of internal ROM from C000016 to FFFFF16. The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30222FG-XXXFP, 20K bytes of internal RAM is mapped to the space from 0040016 to 053FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Tables 1.5 to 1.9 show the location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes.
SFR area For details, see Tables 1.5-1.9 0040016 Internal RAM area XXXXX16
0000016
FFE0016
Special page vector table
Internal reserved area D000016 YYYYY16 Internal ROM area FFFFF16
FFFDC16
Type No. M30222MG/FG/GP
Address XXXXX16 Address YYYYY 16 053FF16 C000016
FFFFF16
Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset
Fig. 1.5. Memory Map
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G CPU
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.6. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15
b0
b15
b0
A1(Note)
SB
Static base register
b15
b0
b15
b0
FB(Note)
Frame base registers
FLG
Flag register
IPL
U
I
OB S Z DC
Note: These registers consist of two register banks.
Fig. 1.6. Central Processing Unit Register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G CPU
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.7 shows the flag register (FLG). The following explains the function of each flag:
* Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged. * Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G CPU
* Bits 8 to 11: Reserved area
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area.
b15
b0
IPL
U
I OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priorit Reserved area
Fig. 1.7. Flag Register
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MITSUBISHI MICROCOMPUTERS
Rev. G Reset
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.8 shows an example reset circuit. Figure 1.9 shows a reset sequence. Table 1.4 shows the pin status when reset pin level is "L".
5V 4.0V VCC 0V 5V RESET 0.8V 0V
RESET
VCC
Example when Vcc = 5V
Fig. 1.8. Example of Reset Circuit
Xin More than 20 cycles are needed
RESET BCLK
BCLK 24cycles
FFFFC16 Address
Content of reset vector
FFFFE16
Fig. 1.9. Reset sequence
Table 1.4. Pin status when Reset pin level is "L"
Pin name
P3, P4 P6 to P10
Status
Input port (with a pull-up resistor) Input port (floating)
SEG0 to SEG23 COM0 to COM3
"H" level is output "H" level is output
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Special function registers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Special function registers
Table 1.5. Location and value after reset of peripheral unit control registers (1)
SFR Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Value after Reset Register Name Acronym
b7 b6 b5 b4 b3 b2 b1 b0
Page Number
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register
PM0 PM1 CM0 CM1 AIER PRCR
0016 0 4816 2016 0 0 0 0 0 0
1.19 1.19 1.23 1.23 1.53 1.34
0
0
Watchdog timer start register Watchdog timer control register Address match interrupt register 0
WDTS WDC RMAD0
0
0
0 0016
1.57 1.57 1.53 1.53 1.53 1.53 1.53 1.53
0 0
Address match interrupt register 1
RMAD1
0016
VDC control register
VDCC
0
0
1.29
DMA0 source pointer
SAR0
?
1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62
DMA0 destination pointer
DAR0
?
DMA0 transfer counter
TRC0
?
DMA0 control register
DM0CON
0
0
0
0
0
0
1.61
DMA1 source pointer
SAR1
?
1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62
DMA1 destination pointer
DAR1
?
DMA1 transfer counter
TCR1
?
DMA1 control register
DM1CON
0
0
0
0
0
0
1.61
? = Undefined
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Special function registers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.6. Location and value after reset of peripheral unit control registers (2)
SFR Address Register Name Acronym Value after Reset
b7 b6 b5 b4 b3 b2 b1 b0
Page Number
004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
INT3 interrupt control register SI/O4 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register Timer B3 interrupt control register INT7 interrupt control register INT6 interrupt control register Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register INT4 interrupt control register Timer A4 interrupt control register INT5 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register SI/O3 interrupt control register
INT3IC S4IC TB5IC TB 4IC TB3IC INT7IC INT6IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC INT4IC TA4IC INT5IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC S3IC
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0
0 0
1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39 1.39
0 0
0 0
0 0 0
0 0 0
010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316
LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD
RAM0 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8 RAM9 RAM10 RAM11 RAM12 RAM13 RAM14 RAM15 RAM16 RAM17 RAM18 RAM19
LRAM0 LRAM1 LRAM2 LRAM3 LRAM4 LRAM5 LRAM6 LRAM7 LRAM8 LRAM9 LRAM10 LRAM11 LRAM12 LRAM13 LRAM14 LRAM15 LRAM16 LRAM17 LRAM18 LRAM19
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146 1.146
012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 013016 013116 013216 013316
LCD mode register Segment output enable register LCD frame frequency counter Key input mode register
LCDM SEG LCDTIM KUPM
0
0
0
0
0
0
0
1.143 1.143 1.143
0016
0
0
1.52
LCD expansion register LCD clock divide counter
LEXP LCDC
0016
1.144 1.144
? = Undefined
1-16
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Special function registers
Table 1.7.
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Location and value after reset of peripheral unit control registers (3)
SFR Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
0016 0016 3F16 3F16
Register Name
Acronym
Value after Reset
b7 b6 b5 b4 b3 b2 b1 b0
Page Number
Timer B3, 4, 5 count start flag
TBSR
0
0
0
1.85 1.94 1.94 1.94 1.92 1.92 1.93 1.93 1.93 1.93
Timer B3 register Timer B4 register Timer B5 register
TB3 TB4 TB5
1.85 1.85 1.85 1.87 1.88, 1.90 1.87 1.88, 1.90 1.87 1.88, 1.90 1.49 1.49 1.138 1.138 1.138 1.138
4016
035B16
Timer B3 mode register
TB3MR
0
0
0
0
0
0
035C16
Timer B4 mode register
TB4MR
0
0
0
0
0
0
035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036C16 036D16 036E16 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Timer B5 mode register Interrupt cause select register 0 Interrupt cause select register 1 SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator Clock divided control register Clock divided counter UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register
TB5MR IFSR0 IFSR1 S3TRR S3C S3BRG S4TRR S4C S4BRG CDCC CDC U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
0
0
0 0016 0016
0
0
0
4016
1.138 1.138 1.24 1.24 1.112 1.130 1.112, 1.134 1.111, 1.130 1.108, 1.114, 1.120 1.107 1.107
0
0016 0016 0016 0016
0816 0216
1.110 1.102
? = Undefined
1-17
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Special function registers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Value after Reset SFR Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
0816 0216 0016
Register Name
Acronym
b7 b6 b5 b4 b3 b2 b1 b0
Page Number
Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register
TABSR CPSRF ONSF TRGSR UDF TA0
0016 0 0 0 0 0 0 0 0
1.71, 1.85, 1.94 1.72, 1.85 1.72 1.72, 1.94 1.71
0016 0016
1.71 TA1 1.71, 1.90 TA2 1.71, 1.90 TA3 1.71 TA4 1.71, 1.90 TB0 1.83 TB1 1.83 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR
0 0 0 0 0 0 0016 0016 0016 0016 0016 0 0 0 0 0 0 0 0 0 0 0 0
1.83, 1.90 1.70, 1.73, 1.77, 1.78 1.70, 1.73, 1.77, 1.78, 1.70, 1.73, 1.77, 1.78, 1.70, 1.72, 1.77, 1.78 1.70, 1.73, 1.77, 1.78, 1.84, 1.87, 1.84, 1.87, 1.84, 1.87, 1.95
1.74, 1.74, 1.95 1.74, 1.95 1.73, 1.74, 1.95 1.90 1.90 1.90,
1.108, 1.114, 1.120 1.107 1.107 1.109 1.110 1.107 1.108, 1.114, 1.120 1.107 1.107 1.109 1.110 1.107 1.111
0016
0816 0216
0
0
0
0
0
0
0
Flash memory control register (Note)
FMCR
0
0
0
1
1.176
DMA0 request cause select register DMA1 CRC data register CRC input register
DM0SL DM1SL CRCD CRCIN
0016 0016
1.60 1.61 1.164 1.164
Note: This register only exists in flash memory version ? = Undefined
1-18
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Special function registers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.9. Location and value after reset of peripheral unit control registers (5) 1.8. (4)
SFR Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 Register Name Acronym
b7 b6
Value after Reset
b5 b4 b3 b2 b1 b0
Page Number
1.154 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 AD0 1.154 AD1 1.154 AD2 1.154 AD3 1.154 AD4 1.154 AD5 1.154 AD6 1.154 AD7
A-D control register 2
ADCON2
0
0
0
0
0
1.154 1.153, 1.155, 1.156, 1.157, 1.158, 1.159 1.153, 1.155, 1.156, 1.157, 1.158, 1.159 1.163 1.163
A-D control register 0
ADCON0
0
0
0
0
0
03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
A-D control register 1 D-A register 0 D-A register 1 D-A control register
ADCON1 DA0 DA1 DACON
0016
0016
1.163
Port P3 Port P3 direction register Port P4 Port P4 direction register Port P6 Port P7 Port P6 direction register Port P7 direction register Port P8 Port P9 Port P8 direction register Port P9 direction register Port P10 Port P10 direction register
P3 PD3 P4 PD4 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
0016
1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170 1.170
0016
0 0
0
0016 0016 0 0 0 0 0016
0 0
0 0
0 0
0016
Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Real-time port control register
PUR0 PUR1 PUR2 RTP
0016 0016 0016 0
0
0
0
1.171 1.171 1.171 1.83
? = Undefined
1-19
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Software Reset
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Figure 1.10 shows processor mode register 0 and 1.
Processor mode register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol PM0
Address 000416
When reset 0016
Bit symbol
Nothing is assigned.
Bit name
Function
RW
Write "0" when writing to this these bits. If read, the value is indeterminate.
The device is reset when this bit is set to "1". The value of this bit is "0" when read.
PM03
Software reset bit
Nothing is assigned. Write "0" when writing to this these bits. If read, the value is indeterminate.
Reserved bit
Must always be set to "0"
Note : Set bit 1 of the protect register (address 000A 16) to "1" when writing new values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol PM1
Address 000516
When reset 0XXXXX002
Bit symbol
Reserved bit
Bit name
Function
Must always be set to "0"
RW
Nothing is assigned. Write "0" when writing to this these bits. If read, the value is indeterminate. PM17 Wait bit 0 : No wait state 1 : Wait state inserted
OO
Note : Set bit 1 of the protect register (address 000A16 ) to "1" when writing new values to this register.
Fig. 1.10. Processor mode register 0 and 1
1-20
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Generating Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.10 shows some examples of the main clock and subclock generating circuits. Table 1.10. Main clock and sub-clock generating circuits
Main clock generating circuit Use of clock Operating clock source for CPU Operating clock source for Internal peripheral Ceramic or crystal oscillator Xin, Xout Available Oscillating Externally derived clock can be input (Note) Sub-clock generating circuit Operating clock source Count clock source for Timers A/B Operating clock source for LCD Crystal oscillator Xcin, Xcout Available Stopped
Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after Reset Other
Note: Max. voltage is the same as VDC
Figure 1.11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.12 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.11 and 1.12 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
Xin (Note) Rd Externally derived clock Xout Open
Xin
Xout
Cin
Cout
Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between Xin and Xout following the instruction.
Fig. 1.11. Examples of main clock
1-21
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Generating Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer
(Built-in feedback resistor)
Microcomputer
Xcin (Note 1) R Xcout Open
Xcin
Xcout
Externally derived clock Ccin Ccout VDC (Note 2) Vss
Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X cin and Xcout following the instruction. Note 2: Reference XCin to VDC supply.
Fig. 1.12. Examples of sub-clock
Figure 1.13 shows a block diagram of the clock generating circuit.
CM14=1 fC1 XCIN CM04 fC Sub clock CM10 "1" Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction Main clock CM02 CM05 XOUT b a c d CM07=0 BCLK fC CM07=1 Divider XCOUT 1/32 fC32 fC132 CM14=0 f1 fAD f8 f32
SQ R
b a
1/2 1/2 1/2 1/2 1/2
c
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10
d
CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16
Details of divider
Fig. 1.13. Clock generating circuit
1-22
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Generating Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from high-speed/ medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction.
(5) fC132
This clock is derived by dividing the sub-clock by 1 or 32. The clock is selected by fC132 clock select bit (bit4 at address 000716). It is used for the Timer A and Timer B counts, intermittent pull up operation of key input.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the Watchdog timer.
Figure 1.14 shows the system clock control registers 0 and 1.
1-23
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Generating Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07
Address 000616 Bit name
Clock output function select bits
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P75 0 1 : fC1 output 1 0 : f1 output 1 1 : Clock divide counter output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 7)
WAIT peripheral function clock stop bit
Xcin-Xout drive capacity 0 : LOW select bit (Note 2) 1 : HIGH
Port Xc Select Bit
0 : I/O port 1 : Xcin - Xcout generation 0 : Main clock on 1 : Main clock off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : Xin, Xout 1 : Xcin, Xcout
Main clock (Xin -Xout ) stop bit (Note 3, 4) Main clock division select bit 0 (Note 6) System clock select bit (Note 5)
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode and at a reset. Note 3: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 4: If this bit is set to "1", Xout turns "H". The built-in feedback resistor remains being connected, so X IN turns pulled up to Xout ("H") via the feedback resistor. Note 5: Set subclock (Xcin - Xcout) enable bit (CM04) to "1" and allow the subclock to stabilize before setting CM07 from from "0" to "1". Do not write to both bits at the same time. Likewise, set the main clock stop bit (CM05) to "0" and allow the subclock to stabilize before settng CM07 bit from "1" to "0". Note 6: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 7: fC, fC132, fC1, fC32 is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note 4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to "0" 0 : fC32 1 : fC1 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit CM14 CM15 CM16 CM17 fC132 clock select bit Xin -Xout drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", Xout goes "H", and the built-in feedback resistor is cut off. Xcin and Xcout goes into high impedance state.
Fig. 1.14. Clock control registers 0 and 1
1-24
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock output
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
The M30222 provides for a clock output signal (P73/CLKOUT pin) of user defined frequency. The clock output function select bit (CM00, CM01) allows you to choose the clock source from f1, fC1, or a divide-byn clock for output to the P73/CLKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Also, the clock divided counter can be controlled for start or stop by the clock divide counter start flag. Figure 1.15 shows a block diagram of clock output. Figure 1.16 shows a clock divided counter related register.
Clock source selection
P75 f1 fC1 P75/CLKOUT
1/2
f32
Clock divided counter (8) Division n+1 n=0016 to FF16 Reload register (8)
Low-order 8 bits
Address 036E16
Data bus low-order bits
Example: When f(XIN)=10MHz, count source = f32 n=0716 : approx. 19.5kHz n=2616 : approx. 4.0kHz n=4D16 : approx. 2.0kHz n=9B16 : approx. 1.0kHz
Fig. 1.15. Block diagram of clock output
Clock divided counter
b7 b0
Symbol CDC
Address 036E16
When reset XX16
Function
8-bit timer
Values that can be set
0016 to FF16
RW
Clock divided counter control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CDCC Bit symbol
Address 036C16 Bit name
When reset 0XXXXXXX2 Function RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is indeterminate.
CDCS
Clock divided counter start flg
0 : Stop 1 : Start
Fig. 1.16. Clock divided counter related register
1-25
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Wait Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and Watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.11 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Usage Precautions
When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1". Table 1.11. Port Status during wait mode
Pin Port CLKOUT/P75
Mode
Single-chip mode Retains status before wait mode Does not stop Retains status before stop mode. Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is maintained.
When fC1 selected When f1, clock divided counter output selected
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Stop Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Stop Mode
Writing "1" to all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, fC, fC132, fC1, fC32 and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, Timer A and Timer B operate provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided an external clock is selected. Table 1.12 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If coming out of stop mode is caused by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Usage Precautions
(1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. Put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1".
Table 1.12 Port status during stop mode
Pin Port CLKOUT/ P75 When fc1 selected When f1, clock divided output selected
Mode
Status Retains status before stop mode "H" Retains status before stop mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Status Transition of BCLK
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow time in software for the source to stabilize before switching over the clock.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Status Transition of BCLK
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.13. Operating modes dictated by settings of system clock control registers 0 and 1
CM17 0 1 Invalid 1 0 Invalid Invalid CM16 1 0 Invalid 1 1 Invalid Invalid CM07 0 0 0 0 0 1 1 CM06 0 0 1 0 0 Invalid Invalid CM05 0 0 0 0 0 0 1 CM04 Invalid Invalid Invalid Invalid Invalid 1 1 BCLK operating mode Divide by 2 Divide by 4 Divide by 8 Divide by 16 None Low-speed Low power dissipation
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Voltage Down Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Voltage Down Converter
The Voltage Down Converter (VDC) is a bandgap reference based voltage regulator used for generating a low-voltage supply. The VDC block inputs the external supply VCC (up to 5.5 volts) and generates a 3.3volt (nominal) supply (VDD). Table 1.14 describes the specified voltage regulation. The VDC is programmable in terms of drive limit and power level. In low power mode, the VDC can source up to 20mA and uses less than 10uA bias current. In high-power mode, the VDC can source up to 200mA. There is a programmable option to limit the current of the VDC in high-power mode to about 80mA. The VDC default state (from reset) is high-power mode with current limiting enabled. The current limiting is enabled at reset in order to avoid a large in-rush current to an external hold capacitor (required) on the VDC pin. Once the external hold capacitor is charged, the current limiter can be disabled in software. Figures 1.17 and 1.18 describe the programmable features of the VDC. The external hold capacitor is required to stabilize the VDC and to minimize voltage ripple on the 3.3 volt supply during operation. Table 1.15 describes the external hold capacitor requirements.
Table 1.14. VDC voltage regulations
Signal Package Supply (Vcc) Internal Supply (Vdd) Description Range: 2.7v to 5.5v (input to VDC) 3.3v (nominal) +/- 10% (output from VDC) OR Vcc - 200mV @ Icc(AVG) <15 mA (Note) Note: Whichever is smaller
Voltage Down Converter control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol VDCC Bit symbol
b1 b0
Address 001816
When reset XXX00X002 Function RW
VDCC0 VDCC1
0 0 : VDC enabled 0 1 : Reserved 1 0 : Reserved 1 1 : VDC disabled
Nothing is assigned. Write "0" when writing to this bit. If read, the value is indeterminate. HPOWER ILIMEN 0 : High power 1: Low power
__
0 : Current limit enabled 1 : Current limit disabled Nothing is assigned. Write "0" when writing to these bits. If read, the value is indeterminate.
__
Figure 1.17. VDC Control/Status Register Table 1.15. Required External Components
Component External Hold Capacitor Value 0.1F +/- 20% Material Ceramic
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Voltage Down Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
EXTERNAL SUPPLY (5 V) Vcc HIGH POWER REGULATOR BANDGAP REFERENCE 3.3 V SUPPLY
(1.22V) EN
Vcc
(0) CURRENT LIMIT
(1)
(1)
(0)
VDCC0 VDCC1
VDC Control HPOWER Status Register
ILIMEN
VDC Pin
0.1 F
EXTERNAL HOLD CAPACITOR
LOW POWER REGULA TOR
Vcc EN
Fig. 1.18. VDC Functional block diagram
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Power Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes. (a) Normal operation mode * High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
* Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
* Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
* Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the subclock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption.
Figure 1.19 is the state transition diagram of the above modes.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Power Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
State Transitions for Stop and Wait modes
RESET
All oscillators stopped
Interrupt
Stop Mode
CM10 = "1"
Medium-speed mode (divided-by-8 mode) High speed / Medium-speed mode
WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt
CPU operation stopped Wait mode CPU operation stopped Wait mode CPU operation stopped Wait mode
All oscillators stopped Stop Mode All oscillators stopped
Interrupt CM10 = "1"
Stop Mode
CM10 ="1"
Low-speed / Low power dissipation mode Normal Mode
State Transitions for normal mode
Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = "1" Main clock is oscillating Sub clock is oscillating BCLK : f(Xin )/8 CM07 = "0" CM06 = "1" CM04 = "0" CM04 = "1" (Notes 1, 3) CM07 = "0" (Note 1) CM06 = "1" CM04 = "0"
High-speed mode BCLK ; f(Xin ) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" Medium-speed mode (divided-by-4 mode) BCLK : f(Xin )/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" CM04 = "0"
Medium-speed mode (divided-by-2 mode) BCLK ; f(Xin )/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-16 mode) BCLK : f(Xin )/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1" Main clock is oscillating Sub clock is stopped
Medium-speed mode (divided-by-8 mode) BCLK : f(Xin )/8 CM07 = "0" CM06 = "1"
CM07 = "0" (Note 1, 3) CM07 = "1" (Note 2)
Main clock is oscillating Sub clock is oscillating Low-speed mode BCLK : f(Xcin) CM07 = "1"
CM05 = "0" CM04 = "1"
CM05 = "1"
High-speed mode BCLK ; f(Xin ) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" CM06 = "0" (Notes 1, 3) Medium-speed mode (divided-by-4 mode) BCLK : f(Xin )/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" Note 1: Note 2: Note 3: Note 4:
Medium-speed mode (divided-by-2 mode) BCLK ; f(Xin )/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-16 mode) BCLK : f(Xin )/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
Main clock is stopped Sub clock is oscillating Low-power dissipation mode CM07 = "1" (Note 2) CM05 = "1" CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1" BCLK : f(Xcin) CM07 = "1"
Switch clock after oscillation of main clock is sufficiently stable. Switch clock after oscillation of sub clock is sufficiently stable. Change CM06 after changing CM17 and CM16. Transit in accordance with arrow.
Fig. 1.19. State Transition diagram of power control mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Software Wait
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". When set to "1", a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Table 1.16 shows the software wait and bus cycles. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to "1".
Table 1.16. Software wait and bus cycles
Area
SFR Internal ROM/RAM
Wait bit Invalid 0 1
Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Protection
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.20 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), Port P9 direction register (address 03F316) and VDC control register (address 001816)can only be changed when the respective bit in the protect register is set to "1". The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXX0000 2 Function
0 : Write-inhibited 1 : Write-enabled 0 : Write-inhibited 1 : Write-enabled 0 : Write-inhibited 1 : Write-enabled
RW
Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) Enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 000516) Enables writing to Port P9 direction register (address 03F3 16) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) (Note) Enables writing to VDC control register (address 001816)
PRC1
PRC2
PRC3
0 : Write-inhibited 1 : Write-enabled
OO
Nothing is assigned. Write "0" when writing to these bits. If read, the value is indeterminate.
Note: Writing a value to these addresses after "1" is written to this bit returns the bit to "0" . Other bits do not automatically return to "0" and they must therefore be reset by the program
Fig. 1.20. Protect register
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of Interrupts
Types of Interrupts
Figure 1.21 lists the types of interrupts.
Undefined instruction (UND instruction) Software Overflow (INTO instruction) BRK instruction INT instruction Interrupt Reset NMI DBC Watchdog timer Single step Peripheral I/O (Note) Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Address matched
Special Hardware
Figure 1.21. Classification of interrupts An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. * Maskable interrupt :
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when an executing arithmetic instruction overflows. The following instructions will set an O flag when an overflow occurs : ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT interrupt An INT interrupt occurs when specifying one of the software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction executes the same interrupt routine as the peripheral I/O interrupt. The stack pointer (SP), used for the INT interrupt, is dependent on which software interrupt number is selected. As far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. The U flag is set to "0" selecting the interrupt stack pointer then the interrupt sequence is executed. When returning from the interrupt routine, the U flag is returned to its previous state before accepting the interrupt request. As far as software numbers 32 through 63 are concerned, the stack pointer does not change.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts Hardware Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset Reset occurs if an "L" is input to the RESET pin. * NMI interrupt An NMI interrupt occurs if an "L" is input to the NMI pin. * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. * DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. * Key-input interrupt A key-input interrupt occurs if an "L" is input to the KI pin. * A-D conversion interrupt This is an interrupt that the A-D converter generates. * SIO3, SIO4 interrupt These are the interrupts for SIO3, SIO4 * UART0, UART1, UART2/NACK transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2/ACK reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through Timer A4 interrupt These are interrupts that Timer A generates * Timer B0 interrupt through Timer B5 interrupt These are interrupts that Timer B generates. * INT0 interrupt through INT7 interrupt An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to one of the INT pins.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, program execution branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.22 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
MSB Vector address + 0 Low address Vector address + 1 Vector address + 2
Vector address + 3
LSB
Mid address 0000 0000 High address 0000
Figure 1.22.
Format for specifying interrupt vector addresses
* Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.17 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.17. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source Undefined instruction Overflow BRK instruction Address match Single step (Note) Watchdog timer DBC (Note) NMI Reset Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 FFFE816 to FFFEB16 FFFEC16 to FFFEF16 FFFF016 to FFFF316 FFFF416 to FFFF716 FFFF816 to FFFFB16 FFFFC 16 to FFFFF16 Remarks Interrupt on UND instruction Interrupt on overflow If thisvector contains FFFFF16, program execution starts from the address shown by the vector in the variable vector table Requires address-matching interrupt enable bit Do not use Do not use External interrupt by input to NMI pin
Note: Interrupts used for debugging purposes only.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts * Variable vector tables
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The addresses in the variable vector table can be modified, according to the user's settings. Before enabling interrupts, the user msut load the INTB register with the address of the first entry in the table. The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.18 shows the interrupts assigned to the variable vector tables and addresses of vector tables. shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.18. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Software interrupt number 0
Vector table address Address (L) to address (H)
+0 to +3 (Note 1)
Interrupt source
BRK instruction
Remarks
Not masked by I flag
~ ~
Software interrupt number 4
+16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to + 63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1)
~ ~
INT3 / SIO4 (Note 3) Timer B5 Timer B4 Timer B3
Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
INT7
INT6 Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit (Note 2) UART2 receive (Note 2) UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3/ INT4 (Note 3) Timer A4 / INT5 (Note 3) Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 / SIO3 (Note 3)
Software interrupt
Not masked by I flag
Note 1: Address relative to address in interrupt table register (INTB). Note 2: When IIC mode is selected, NACK and ACK interrupts are selected. Note 3: Selected by Interrupt Request Cause Select bit (bits 4, 5, 6, 7 at address 035F16)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bits, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the CPU flag register (FLG). Figure 1.23 shows the memory map of the interrupt control registers.
Interrupt control register (Note 1)
Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 2) TBiIC(i=0 to 2) Address 0045 16 to 004716 004A16 004B16, 004C16 004D16 004E16 0051 16 005316, 004F16 0052 16, 005416, 005016 0055 16 to 005716 005A 16 to 005C16 When reset XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 XXXX0000 2 R W
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Bit name
b2 b1 b0
Function
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : Level Level Level Level Level Level Level Level 0 (interrupt disabled) 1 2 3 4 5 6 7
ILVL1
Interrupt priority level select bit
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 2)
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". Note 1: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Symbol INTiIC(i=0 to 1) INT2IC/SI3IC INT31C/SI4IC INT4IC/TA3IC INT5/TA4IC INTiIC(i= 6 to 7) Address 005D16 , 005E16 005F16 004416 005816 005916 004916, 004816 When reset XX000000 2 XX000000 2 XX000000 2 XX000000 2 XX000000 2 XX000000 2 R W
b7
b6
b5
b4
b3
b2
b1
b0
0
Bit symbol
ILVL0 ILVL1
Bit name
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0: Selects falling edge 1: Selects rising edge Always set to "0"
Interrupt priority level select bit
ILVL2 IR POL Interrupt request bit Polarity select bit
(Note 2)
Reserved bit
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0". Note 1 To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Figure 1.23. Memory map of the interrupt control registers.
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts Interrupt Enable Flag (I flag)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bits, which consists of three interrupt control register bits. When an interrupt request occurs, the interrupt priority level is compared with the IPL of the CPU flag register. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 1.19 shows the settings of interrupt priority levels and Table 1.20 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: *interrupt enable flag (I flag) = 1 *interrupt request bit = 1 (set by hardware) *interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.19. Settings of interrupt priority levels Table 1.20. Interrupt levels enabled according to the contents of the IPL
Interrupt priority level select bit
b2 b1 b0
Interrupt priority level
Priority order
IPL
IPL2 IPL1 IPL0
Enabled interrupt priority levels
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts Modifying the interrupt control register
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When modifying the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is a possibility of the interrupt request occurring, access the interrupt control register after the interrupt is disabled. The program examples are described below:
Example 1: INT_SWITCH1: FCLR AND.B NOP NOP FSET Example 2: INT_SWITCH2: FCLR AND.B MOV.W FSET Example 3: INT_SWITCH3: PUSHC FCLR AND.B POPC FLG I #00h, 0055h FLG ;Push Flag register onto stack ;Diable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Enable interrupts. I #00h, 0055h MEM, R0 I :Disable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Dummy read. ;Enable interrupts. I #00h, 0055h :Disable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Four NOP instructions are required when using the HOLD function. ;Enable interrupts.
I
The reason why two NOP instructions (four using the HOLD function) or dummy read is inserted before FSET I in Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to the effects of the instruction queue.
When modifying an interrupt control register, it is recommended to use only the instructions: AND, OR, BCLR and BSET. Using the "MOV" or other instruction may cause an interrupt to be missed.
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
The interrupt sequence, described below, is performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The processor carries out the following in sequence after an interrupt request:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (2) Saves the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the contents of the temporary register (Note) within the CPU in the stack area. (5) Saves the contents of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.24 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.
Figure 1.24. Interrupt response time
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.21. Table 1.21. Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd 16-bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 8-bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt. Add 1 cycle in the case of either an address coincidence interrupt or a single-step interrupt. Note 2: If possible, locate an interrupt vector address in an even address.
Figure 1.25 shows the time required for executing the interrupt sequence
1 BCLK
2
3
4
5
6
7
8
9
10
11
12
Internal Address bus
Address 0000
Indeterminate
SP-2
SP-4
PC
Internal Data bus
Interrupt information
Indeterminate
SP-2 contents
SP-4 contents
The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs.
Fig. 1.25. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.22 is set in the IPL. Table 1.22. Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels Watchdog timer, NMI RESET Other Value set in the IPL 7 0 No change
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts Saving Registers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.26 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB
Stack area LSB
Address MSB
Stack area LSB [SP] New stack pointer
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m-4 m-3 m-2 m-1 m m+1
Program counter (PC L) Program counter (PCM) Flag register (FLG L) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 1.26. State of stack before and after acceptance of interrupt request
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.27 shows the operation of the saving registers. Note: When any INT instruction in software number 32 to 63 is executed, the stack pointer is indicated by the U Flag, otherwise, it is the interrupt stack pointer (ISP)
(1) Stack pointer (SP) contains even number
Address Stack area Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3 (Odd) [SP] - 2 (Even) [SP] - 1 (Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PC L) Program counter (PC M) Flag register (FLG L) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) Stack pointer (SP) contains odd number
Address Stack area Sequence in which order registers are saved
[SP] - 5 (Even) [SP] - 4 (Odd) [SP] - 3 (Even) [SP] - 2 (Odd) [SP] - 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PC L) Program counter (PC M) Flag register (FLG L) Flag register (FLGH) Program counter (PCH)
(3) (4) (1) (2)
Saved simultaneously, all 8 bits
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 1.27. Operation of saving registers
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bits. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control is distributed to the interrupt routine. Figure 1.28 shows the priorities of hardware interrupts.
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.28. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.29 shows the circuit that judges the interrupt priority level.
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3/INT4 Timer A1 Timer B4 INT3/SI04 INT2/SI03 INT0 Timer B1 Timer A4/INT5 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection INT7 Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 INT6
Level 0 (initial value)
High
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Interrupt enable flag (I flag)
Address match
Interrupt request accepted
Watchdog timer DBC NMI Reset
Figure 1.29. Maskable interrupts priorities (peripheral I/O interrupts)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts INT Interrupt
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT0 to INT7 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. The interrupt control registers, 005816 is used both as Timer A3 and external interrupt INT4 input control register, and 005916 is used both as Timer A4 and as external interrupt INT5 input control register. Also, 005F16 is used as both SIO3 and external interrupt INT2 input control register and 004416 is used as both SIO4 and external interrupt INT3 input control register. Use the interrupt request cause select bits - bits 4, 5, 6 and 7 of the interrupt request cause select register 0 (address 035E16) - to specify which interrupt request cause to select. When INT4 is selected as an interrupt source, the input port for it can be selected by bits 0 and 1 of the interrupt source select register 0 (address 035E16). Similarly, when INT5 is selected as an interrupt source, the input port for it can be selected by bits 2 and 3 of the interrupt source select register 0 (address 035E16). After having set an interrupt request cause and interrupt input ports, be sure to set the corresponding interrupt request bit to "0" before enabling an interrupt. The interrupt control registers - 005816, 005916, 005F16, and 004416 - have the polarity-switching bit. Be sure to set this bit to "0" to select a timer or SIO as the interrupt request cause. The external interrupt input can be generated both at the rising edge and at the falling edge by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register 1 (035F16). To select two edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). When INT4 input pin select bits = "11", INT4 interupt polarity switching bit = "0", and polarity select bit = "1" of the INT4 interrupt control register, an interrupt is generated by a rising edge on the input port when the exclusive pin is "H", as shown by "Single edge, Rise" in Figure 1.32. When the exclusive pin is "H", interrupts can only be generated by an active transition on a single edge. The same applies to INT5. Figure 1.30 shows the Interrupt request cause select registers. Figure 1.31 shows the block diagram of INT4 and INT5.
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt request cause select register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR0
Bit symbol
Address 035E16
When reset 0016
Bit name
INT4 input pin select bit
Fumction
0 0 : No INT4 input 0 1 : P7 6 input enable 1 0 : P7 7 input enable 1 1 : P7 6, P77 input enable 0 0 : No INT5 input 0 1 : P8 0 input enable 1 0 : P8 1 input enable 1 1 : P8 0, P81 input enable 0 : SIO3 1 : INT2 0 : SIO4 1 : INT3 0 : Timer A3 1 : INT4 0 : Timer A4 1 : INT5
RW
IFSR00 IFSR01 IFSR02 INT5 input pin select bit IFSR03 IFSR04 IFSR05 IFSR06 IFSR07 Interrupt request cause select bit Interrupt request cause select bit Interrupt request cause select bit Interrupt request cause select bit
Interrupt request cause select register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR1
Bit symbol
Address 035F16
When reset 0016
Bit name
INT0 interrupt polarity swiching bit INT1 interrupt polarity swiching bit INT2 interrupt polarity swiching bit INT3 interrupt polarity swiching bit INT4 interrupt polarity swiching bit INT5 interrupt polarity swiching bit INT6 interrupt polarity swiching bit INT7 interrupt polarity swiching bit
Function
0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges 0 : Single edge 1 : Both edges
RW
IFSR10 IFSR11 IFSR12 IFSR13 IFSR14 IFSR15 IFSR16 IFSR17
Figure 1.30. Interrupt request cause select register
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TAiOUT/INTi+1
Interrupt edge select bit
i= 3, 4
TAiN/INTi+1
Two edge detect
Interrupt edge
INTi+1 input pin select bit
Two edge detect
Interrupt request
Figure 1.31. INT4 and INT5 block diagram
Polarity select bit (bit4 of interrupt control register)
0: Falling edge
(Bits 4, 5 of interrupt request cause select register 1)
1: Rising edge
Figure 1.32. Typical timing of interrupts INT4 and INT5
INT4, INT5 interrupt polarity switching bit
"H"
0: One edge 1: Two edges
"H" "L" "H" "L"
"L" "H" "L"
"H" "L" "H" "L"
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
NMI Interrupt
An NMI interrupt is generated when the input to the P83/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P83 register (bit 3 at address 03F016). This pin cannot be used as a normal port input. (See Interrupt Precautions section).
Key Input Interrupt
All bits of Port 6 can be used as Key Input interrupts. Enable the interrupts using the KUPIC register, then set the direction register of any of P60 to P67 bits for input, and a falling edge to that port will generate a key input interrupt. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.33 shows the block diagram of the key input interrupt. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.
Port P60-P67 pull-up select bit Pull-up transistor Port P67 direction register Port P67 direction register P67/KI7 Pull-up transistor P66/KI6 Pull-up transistor Port P65 direction register
Two edge detect "1" "0" Two edge detect "1" "0"
Key input interrupt control register (address 004D16)
Port P66 direction register
Two edge detect "1" "0"
P65/KI5 Pull-up Port P64 direction register transistor P64/KI4
Two edge detect
Interrupt control circuit
Key input interrupt request
P6 Key input enable bit
"1" "0"
Pull-up Port P60 direction register transistor P60/KI0
Two edge detect
"1" "0"
Figure 1.33. Block diagram of key input interrupt
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.34 shows the Key input mode register. With bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for P6. Port P6 is set for pull-up using the pll-up control register.
Key input mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KUPM Bit symbol P6KIS P6KIE
Address 012616 Bit name P6 key input select bit (Note) P6 key input enable bit
When reset XXXXXX00 2 Function 0 : Falling edge 1 : Two edges 0 : Disable 1 : Enable RW
Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate when read. Note :
__
If this bit is set for "Two edges" when the corresponding port has been specified to have a pull up, the port is automatically pulled high intermittently by the operating subclock. The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register
Fig. 1.34. Key input mode register
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Specifications in this manual are tentative and subject to change
Rev. G Overview of Interrupts Address Match Interrupt
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The stack value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure 1.35 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned.
Write 0 when writing to these bits. If read, the value is indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt Nothing is assigned.
Values that can be set R W 0000016 to FFFFF16
Write 0 when writing to these bits. If read, the value is indeterminate.
Figure 1.35. Address match interrupt-related registers.
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MITSUBISHI MICROCOMPUTERS
Rev. G Interrupt Precautions
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
* When a maskable interrupt occurs, the CPU reads the interrupt information (the interrupt number and interrupt request level)from address 0000016 in the interrupt sequence. The interrupt request bit of the interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software enables the highest priority interrupt source request bit. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
(2) Setting the stack pointer
* The stack pointers immediately after reset are initialized to 000016. The stack pointers must nbe set to valid RAM areas for proper operation. An interrupt occurring immediately after reset will cause a runaway condition.
(3) The NMI interrupt
*The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused. * The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input. * Do not reset the CPU with the input to the NMI pin being in the "L" state. * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is ignored. * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. * Minimum NMI pulse width is 1 BCLK cycle.
(4) External interrupts
* A minimum of 250ns pulse width is necessary for the signal input to pins INT0 through INT7 regardless of the CPU operation clock. * When the polarity of the INT0 to INT7 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.36 shows the procedure for changing the INT interrupt generate factor.
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Rev. G Interrupt Precautions
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear the interrupt enable flag to "0" (Disable interrupt)
Set the interrupt priority level to level 0 (Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to "1" (Enable interrupt)
Figure 1.36. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
* To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described below:
Example 1: INT_SWITCH1: FCLR AND.B NOP NOP FSET Example 2: INT_SWITCH2: FCLR AND.B MOV.W FSET Example 3: INT_SWITCH3: PUSHC FCLR AND.B POPC FLG I #00h, 0055h FLG ;Push Flag register onto stack ;Diable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Enable interrupts. I #00h, 0055h MEM, R0 I :Disable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Dummy read. ;Enable interrupts. I #00h, 0055h :Disable interrupts. ;Clear TA0IC int. priority level and int. request bit. ;Four NOP instructions are required when using the HOLD function. ;Enable interrupts.
I
The reason why two NOP instructions (four using the HOLD function) or dummy read is inserted before FSET I in Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to the effects of the instruction queue.
* When modifying an interrupt control register, it is recommended to use only the instructions: AND, OR, BCLR, BSET. Using the "MOV" or other instruction may cause an interrrupt to be missed.
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Specifications in this manual are tentative and subject to change
Rev. G Watchdog Timer
M30222 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
The Watchdog timer has the function of detecting when the program is out of control. The Watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A Watchdog timer interrupt is generated when an underflow occurs in the Watchdog timer. When XIN is selected for the BCLK, bit 7 of the Watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the Watchdog timer control register (address 000F16). Thus the Watchdog timer's period can be calculated as given below. The Watchdog timer's period is, however, subject to an error due to the prescaler.
With XIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X Watchdog timer count (32768) BCLK
With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X Watchdog timer count (32768) BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the Watchdog timer's period becomes approximately 32.8 ms. The Watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a Watchdog timer interrupt request is generated. The prescaler must be set before initializing the Watchdog timer. Once initialized, the Watchdog timer can only be stopped by a reset. The counter is reset to 7EEE16 by writing any value to the Watchdog timer start register (address 000E16). Figure 1.37 shows the Watchdog timer block diagram. Figure 1.38 shows the Watchdog timer-related registers.
Prescaler
"CM07 = 0" "WDC7 = 0"
1/16
BCLK HOLD
"CM07 = 1"
1/128
"CM07 = 0" "WDC7 = 1"
Watchdog timer
Watchdog timer interrupt request
1/2
Write to the watchdog timer start register (address 000E16)
Set to "7FFF16"
RESET
Fig. 1.37. Block diagram of Watchdog timer
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Watchdog Timer
M30222 Group
SINGLE-CHIP16-BIT CMOS MICROCOMPUTER
Watchdog timer control register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol
Address 000F16 Bit name
When reset 000XXXXX2 Function RW
High-order bit of Watchdog timer Reserved bit
WDC7
Must always be set to "0" Prescaler select bit 0 : Divided by 16 1 : Divided by 128
Note: Set the desired prescale value before initializing the Watchdog timer.
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate RW
Function
The Watchdog timer is initialized and starts counting after the first write instruction to this register after reset. Writing any value to this register resets the counter to 7FFF16.
Fig. 1.38. Watchdog timer control and start registers
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. The DMAC shares the same data bus with the CPU. The DMAC uses a high speed cycle-stealing method because it has a higher right to use the bus than the CPU. DMA transfers word (16-bit) or a byte (8-bit) data. Figure 1.39 shows the block diagram of the DMAC. Table 1.23 shows the DMAC specifications. Figures 1.40 to 1.42 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20) (addresses 0022 16 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 0026 16 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 0032 16 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 0036 16 to 003416)
(addresses 0029 16, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 0039 16, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.39. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. The DMA transfers are not affected by the interrupt enable flag (I flag) or by the interrupt priority level and the DMA transfer doesn't affect any interrupt. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
Table 1.23. DMAC specifications
Item Number of channels Transfer memory space
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specification 2 (cycle-stealing method) From any address in the 1m byte space to a fixed address From a fixed address to any address in the 1 M byte space From a fixed address to a fixed address DMA-related registers (002016 to 003F16) cannot be accessed 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) Falling edge of INT0 or INT1or both edges (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to Timer A4 interrupt requests Timer B0 to Timer B5 interrupt requests UART0 transfer and receive interrupt requests UART1 transfer and receive interrupt requests UART2 transfer and receive interrupt requests Serial I/O 3,4 interrupt requests A-D conversion interrupt requests Software triggers DMA0 has priority if DMA0 and DMA1 requests are generated simultaneously 8 bit or 16 bit Forward/Fixed (Forward direction cannot be specified for both source and destination simultaneously) Single transfer mode After the transfer counter underflows, the DMA enable becomes 0 and the DMAC becomes inactive. Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a 0 is written to the DMA enable bit. When an underflow occurs in the transfer counter When the DMA enable bit is set to 1 , the DMA is active. When the DMA is active, data transfer starts each time the DMA transfer request signal occurs. When the DMA enable bit is set to 0 , the DMAC is inactive. After the transfer counter underflows in single transfer mode. When the DMAC is enabled, the DMA source pointer is loaded to the DMA forward address pointer. The DMA transfer load pointer is copied to the DMA transfer counter at that time. Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write enabled when the DMA enable bit is 0 . Can be read anytime. However, when the DMA enable bit is 1 , reading the register set up as the forward register is the same as reading the value of the forward address pointer.
Maximum number of bytes transferred DMA request factors (Note)
Channel priority Transfer unit Transfer address direction
Transfer mode
DMA interrupt request generation timing Active
Inactive
Forward address pointer and reload timing for transfer counter
Writing to register
Reading the register
Note: DMA transfers do not effect any interrupt and are not affected by the interrupt enable flag (I flag) or by any interrupt priority level.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL
Address 03B816
When reset 0016
Bit symbol
Bit name
b3 b2 b1 b0
Function (Note)
0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit
R
W
DSEL0 1 : Expanded cause DSEL1 DMA request cause select bits
DSEL2
DSEL3 Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
DMS DMA request cause expansion bit Software DMA request bit 0: Normal 1: DMA caused by setting DSEL0 to DSEL3 (Expanded cause) If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
DSR
Note: When the selected functions of the interrupt request are set, a DMA transfer request will occur.
Fig. 1.40. DMAC register (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM1SL
Address 03BA16
When reset 0016
Bit symbol
Bit name
b3 b2 b1 b0
Function (Note)
0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 (DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0)/two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit
R
W
DSEL0
DSEL1 DMA request cause select bits DSEL2
DSEL3 Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
DMS DMA request cause expansion bit Software DMA request bit 0: Normal 1: DMA is caused by setting DSEL0 to DSEL3 (Expanded cause) If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value is always "0")
DSR
Note: When the selected functions of the interrupt request are set, a DMA transfer request will occur.
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiCON(i=0,1)
Address 002C16, 003C16
When reset XX0000002
Bit symbol DMBIT DMASL DMAS DMAE DSD DAD
Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits
Function
R
W
0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward
(Note 2)
Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously.
Fig. 1.41. DMAC register (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016 Transfer count specification
When reset Indeterminate Indeterminate
Function * Source pointer Stores the source address
Nothing is assigned.
RW
0000016 to FFFFF16
Write "0" when writing to these bits. If read, the value is "0".
DMAi destination pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416 Transfer count specification
When reset Indeterminate Indeterminate
Function * Destination pointer Stores the destination address
Nothing is assigned.
RW
0000016 to FFFFF16
Write "0" when writing to these bits. If read, the value is "0".
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
When reset Indeterminate Indeterminate RW
Function * Transfer counter Set a value one less than the transfer count
Transfer count specification 000016 to FFFF16
Fig. 1.42. DMAC register (3)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination starts at odd addresses, there is one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.43 shows the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) 8-bit transfers 16-bit transfers from even address and the source address is even.
BCLK Address bus RD WR Data bus
CPU use Source Destination CPU use Source Destination
Note 2
CPU use
Note 2
CPU use
(2) 16-bit transfers and the source address is odd
BCLK Address bus RD WR Data bus
CPU use Source Source + 1 Destination CPU use Source Source + 1 Destination
Note 2
CPU use
Note 2
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK Address bus RD WR Data bus
CPU use Source Destination CPU use Source Destination
Note 2
CPU use
Note 2
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
BCLK Address bus RD WR Data bus
CPU use Source Source + 1 Destination CPU use Source Source + 1 Destination
Note 2
CPU use
Note 2
CPU use
Note 1: The same timing changes occur with the respective conditions at the destination as at the source. Note 2: This cycle may be added depending on the instruction queue.
Fig. 1.43. Example of the transfer cycle for a source read
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.24 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.24. No. of DMAC transfer cycles
Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Coefficient j, k
Bus width 16-bit (BYTE= "L") 16-bit (BYTE = "L")
Access address Even Odd Even Odd
No. of read cycles 1 1 1 2
No. of write cycles 1 1 1 2
Internal memory Internal ROM/RAM No Wait 1 Internal ROM/RAM SFR area With Wait 2 2
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit.
DMA request bit
The DMA request bit is set by a DMA transfer request signal. This signal is triggered by a factor selected in advance by the DAMi Request Cause select bits. DMA request factors include the following:
*Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". Be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. The timing of changes in the DMA request bit is explained below. (1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Direct Memory Access Controller (2) External factors
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. Figure 1.44 shows an example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur.
Example of DMA transmission that is carried out in minimum cycles at the time DMA transmission occur concurrently.
BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit
/////////// /////////// ///////////////// /////// //////////////
Bus control
Fig. 1.44. An example of DMA transfer affected by external factors
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers
There are eleven 16-bit timers. These timers can be classified by function into Timers A (five) and Timers B (six). All these timers function independently. Figures 1.45 and 1.46 show the block diagram of timers.
Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 XCIN 1/32 Reset fC32
Clock prescaler reset flag (bit 7 f32 at address 038116) set to "1"
* Timer mode * One-shot mode * PWM mode
Timer A0 interrupt TA0 IN
Noise filter
Timer A0
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Port 3 real-time output trigger
Timer A1 interrupt Timer A1
TA1 IN
Noise filter
* Event counter mode * Timer mode * One-shot mode * PWM mode
Port 4 real-time output trigger
Timer A2 interrupt TA2 IN
Noise filter
Timer A2
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A3 interrupt TA3 IN
(Note 1)
Noise filter
Timer A3
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A4 interrupt TA4 IN
(Note 2)
Noise filter
Timer A4
* Event counter mode
Timer B2 overflow
Note 1: The TA3 IN pin (P77) is shared with INT4 pin. Note 2: The TA4 IN pin (P81) is shared with INT5 pin.
Figure 1.45. Timer A block diagram
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timers
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 Timer A f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" 1/32 Reset fC32
* Timer mode * Pulse width measuring mode
TB0IN
(Note 1)
Noise filter
Timer B0 interrupt Timer B0
* Event counter mode
* Timer mode * Pulse width measuring mode
TB1IN
Noise filter
Timer B1 interrupt
Timer B1
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B2 interrupt
TB2IN
Noise filter
Timer B2
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B3 interrupt
TB3IN
Noise filter
Timer B3
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B4 interrupt
TB4IN
Noise filter
Timer B4
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B5 interrupt
TB5IN
Noise filter
Timer B5
* Event counter mode
Note 1: The TB0IN pin (P90) is shared with INT2 pin
Figure 1.46. Timer B block diagram
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.47 shows the block diagram of Timer A. Figures 1.48 to 1.50 show the Timer A-related registers. Except in event counter mode, Timers A0 through A4 all have the same function. Use the Timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. * Real-time port mode.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC32
Polarity selection
TAi IN (i = 0 to 4)
* Timer * One shot * PWM * Timer (gate function) * Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection
Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
Count start flag
(Address 038016) Down count External trigger
TB2 overflow TAj overflow
(j = i - 1. Note that j = 4 when i = 0) (k = i + 1. Note that k = 0 when i = 4)
Up/down flag
(Address 038416)
TAk overflow TAi OUT
(i = 0 to 4) Pulse output
Toggle flip-flop
Fig. 1.47. Block diagram of Timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TAiMR(i=0 to 4)
Address When reset 0016 039616 to 039A16
Bit symbol
TMOD0
Bit name
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
Operation mode select bit
TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Fig. 1.48. Timer A-related registers (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4
Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Function * Timer mode Counts an internal count source * Event counter mode Counts pulses from an external source or timer overflow * One-shot timer mode Counts a one shot width * Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator
Values that can be set
RW
000016 to FFFF16 000016 to FFFF16
000016 to FFFF16
000016 to FFFE16 0016 to FE16 (Both high-order and low-order addresses)
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset 0016
Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P
Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to "0"
RW
TA3P TA4P
Fig. 1.49. Timer A-related registers (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset 00X000002
Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is "0"
RW
Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate.
b7 b6
TA0TGL TA0TGH
Timer A0 event/trigger select bit
0 0 1 1
0 1 0 1
: : : :
Input on TA0 IN is selected (Note)
TB2 overflow is selected TA4 overflow is selected TA1 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol TA1TGL TA1TGH TA2TGL
Bit name
b1 b0
Function 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : : : : :
Input on TA1 IN is selected (Note)
RW
Timer A1 event/trigger select bit
TB2 overflow is selected TA0 overflow is selected TA2 overflow is selected
Input on TA2 IN is selected (Note)
b3 b2
Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH
TB2 overflow is selected TA1 overflow is selected TA3 overflow is selected
Input on TA3 IN is selected (Note)
b5 b4
Timer A3 event/trigger select bit
TB2 overflow is selected TA2 overflow is selected TA4 overflow is selected
Input on TA4 IN is selected (Note)
b7 b6
Timer A4 event/trigger select bit
TB2 overflow is selected TA3 overflow is selected TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Fig. 1.50. Timer A-related registers (3)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.25.) Figure 1.51 shows the Timer Ai mode register in timer mode. Usage Precautions
Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16". Reading the Timer Ai register after setting a value in theTimer Ai register with a count halted but before the counter starts counting gets a proper value. Table 1.25. Timer mode specifications
Item Count source Count operation f1, f8, f32, fc32 Count down When the timer underflows, it reloads the reload register contents before counting continues. 1/(n+1) n: Set value Specification
Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Count start flag is set (=1) Count start flag is reset (=0) When timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading Timer Ai register When counting stops When a value is written to Timer Ai register, it is written to both reload register and counter When counting is in progress When a value is written to Timer Ai regiser, it is written to only reload register (Transferred to counter at next reload time). Gate function Counting can be started and stopped by the TAiIN pin s input signal. Pulse output function Each timer the timer underflows, the TAiOUT pin s polarity is reversed.
Select function
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0
Address 039616 to 039A16 Bit name
When reset 0016 Function
b1 b0
RW
Operation mode select bit Pulse output function select bit
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA iOUT pin is a pulse output pin)
b4 b3
MR1 Gate function select bit MR2 MR3 TCK0 Count source select bit TCK1
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3)
0 (Must always be fixed to "0" in timer mode)
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0".
Fig. 1.51. Timer Ai mode register in timer mode
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.26 lists timer specifications when counting a single-phase external signal. Figure 1.52 shows the Timer Ai mode register in event counter mode. Table 1.27 lists timer specifications when counting a two-phase external signal. Figure 1.53 shows the Timer Ai mode register in event counter mode. Usage Precautions
(1) Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the Timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the Timer Ai register after setting a value in the Timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.26. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item Count source Count operation Specification External signals input to TAiIN pin (effective edge can be selected by software) TB2 overflow, TAj overflow Up count or down count can be selected by external signal or software. When the timer overflows or underflows, it reloads the reload register contents before counting continues (Note) 1/(FFFF16 - n+1) for up count 1/(n + 1) for down count Count start flag is set (=1) Count start flag is reset (=0) The timer overflows or underflows. Programmable I/O port or count source input Programmable I/O port or pulse output, or up/down count select input Count value can be read out by reading Timer Ai register When counting stops When a value is written to Timer Ai register, it is written to both reload register and counter When counting is in progress When a value is written to Timer Ai register, it is written to only reload register (Transferred to counter at next reload time). Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it. Pulse output function Each timer the timer overflows or underflows, the TAiOUT pin s polarity is reversed.
Divide ratio
n: Set value
Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Select function
Note: This does not apply when the free-fun function is selected.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TAiMR(i = 0, 1) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Address 039616, 039716
When reset 0016 Function RW
Bit name Operation mode select bit
b1 b0
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TA iOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 4)
Pulse output function select bit Count polarity select bit (Note 3) Up/down switching cause select bit
0 (Must always be fixed to "0" in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0".
Fig. 1.52. Timer Ai mode register in event counter mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.27. Timer specifications in event counter mode (when processing two-phase pulse signal with Timers A2, A3,and A4)
Item Count source Count operation
Specification * Two-phase pulse signals input to TAi IN or TAi OUT pin * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note)
Divide ratio Count start condition Count stop condition
Interrupt request generation timing
1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading Timer A2, A3, or A4 register * When counting stopped When a value is written to Timer A2, A3, or A4 register, it is written to both reload register and counter * When counting in progress When a value is written to Timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation The timer counts up rising edges or counts down falling edges on the TAi IN pin when input signal on the TAi OUT pin is "H" n : Set value
TAi IN pin function TAi OUT pin function Read from timer Write to timer
Select function
TAi OUT TAi IN (i=2,3)
Up Count Up Count
Up Count
Down Count
Down Count
Down Count
* Multiply-by-4 processing operation If the phase relationship is such that the TAi IN pin goes "H" when the input signal on the TAi OUT pin is "H", the timer counts up rising and falling edges on the TAi OUT and TAi IN pins. If the phase relationship is such that the TAi IN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges Count down all edges
TAiIN (i=3,4)
Count up all edges Count down all edges
Note: This does not apply when the free-run function is selected
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016
Bit symbol
TMOD0 TMOD1 MR0
Bit name
b1 b0
Function
0 1 : Event counter mode 0 : Pulse is not output (TAi OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAi OUT pin is a pulse output pin) 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 3)
RW
Operation mode select bit
Pulse output function select bit Count polarity select bit (Note 2) Up/down switching cause select bit
MR1 MR2 MR3 TCK0 TCK1
0 : (Must always be "0" in event counter mode) Count operation type select bit Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to "0". Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0 "or "1". Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 0382 16 and 038316) to "00".
Timer Ai mode register (When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol Address When reset 0016 TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be "0" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) 1 (Must always be "1" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note 1: This bit is valid for Timer A3 mode register. For Timer A2 and A4 mode registers, this bit can be "0" or "1". Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Always be sure to set the event/trigger select bit (address 038216 ) to "00".
Fig. 1.53. Timer Ai mode register in event counter mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot timer mode
In this mode, the timer operates only once as shown in Table 1.28. When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.54 shows the Timer Ai mode register in one-shot timer mode. Usage Precautions
(1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the Timer Ai interrupt request bit goes to "1". (2) The Timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to useTimer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. Table 1.28. Timer specifications in one-shot timer mode
Item Count source Count operation f1, f8, f32, fc32 Timer counts down When the count reaches 000016, the timer stops counting after reloading a new count. If a trigger occurs when counting, the timer reloads a new count and restarts counting. 1/n n: Set value An external trigger is input Timer overflows One-shot start flag is set (=1) A new count is reloaded after the count has reached 000016 The count start flag is reset (=0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When Timer Ai register is read, it indicates an indeterminate value. When counting stops When a value is written to Timer Ai register, it is written to both reload register and counter When counting is in progress When a value is written to Timer Ai register, it is written to only reload register (Transferred to counter at next reload time). Specification
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset 0016 TAiMR(i = 0 to 4) 039616 to 039A16 Bit symbol TMOD0 TMOD1 MR0 Bit name
b1 b0
Function
RW
Operation mode select bit 1 0 : One-shot timer mode Pulse output function select bit External trigger select bit (Note 2) Trigger select bit 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAi OUT pin is a pulse output pin)
0 : Falling edge of TAi IN pin's input signal (Note 3) 1 : Rising edge of TAi IN pin's input signal (Note 3)
MR1 MR2 MR3 TCK0
0 : One-shot start flag is valid 1 : Selected by event/trigger select register
0 (Must always be "0" in one-shot timer mode)
b7 b6
Count source select bit TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (address 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0".
Fig. 1.54. Timer Ai mode register in one-shot timer mode
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.29.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.55 shows theTimer Ai mode register in pulse width modulation mode. Figure 1.56 shows the example of how a 16-bit pulse width modulator operates. Figure 1.57 shows the example of how an 8-bit pulse width modulator operates. Usage Precautions
(1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to useTimer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the Timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and theTimer Ai interrupt request bit does not becomes "1".
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.29. Timer specifications in pulse width modulation mode
Item Count source Count operation f1, f8, f32, fc32 Timer counts down (operating as an 8-bit or 16-bit pulse modulator) Timer reloads new count at a rising edge of PWM pulse and continues counting. Timer is not affected by a trigger that occurs when counting. High level width Cycle time High level width Cycle time n/fi (216-1)/fi n: Set value fixed Specification
16-bit PWM
8-bit PWM Count start condition
n x (m + 1)/fi n: values set Timer Ai s high-order address (28-1) x (m+1)/fi m: values set Timer Ai s low-order address
External trigger is input Timer overflows Count start flag is set (=1) Count start flag is reset (=0) PWM pulse goes L Programmable I/O port or trigger input Pulse output When Timer Ai register is read, it indicates an indeterminate value. When counting stops When a value is written to Timer Ai register, it is written to both reload register and counter. When counting is in progress When a value is written to Timer Ai register, it is written to only reload register (Transferred to counter at next reload time).
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1
Address When reset 039616 to 039A16 0016 Function
b1 b0
Bit name Operation mode select bit 1 1 : PWM mode
RW
1 (Must always be "1" in PWM mode) External trigger select bit (Note 1) Trigger select bit 16/8-bit PWM mode select bit
0: Falling edge of TAi IN pin's input signal (Note 2) 1: Rising edge of TAi IN pin's input signal (Note 2)
MR2 MR3
0: Count start flag is valid 1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
TCK0 Count source select bit TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0".
Note 2: Set the corresponding port direction register to "0".
Fig. 1.55. Timer Ai mode register in pulse width modulation mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition
: Reload register = 0003 16 , when external trigger (rising edge of TA iIN pin input signal) is selected
1 / fi X (2 16 - 1)
Count source
TA iIN pin input signal
"H" "L"
Trigger is not generated by this signal Note: n = 0000 1 / fi X n
PWM pulse output from TA iOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
Fig. 1.56. Example of how a 16-bit pulse width modulator operates
Condition :
Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected
8
1 / fi X (m + 1) X (2 - 1) Count source (Note1)
TA iIN pin input signal
"H" "L"
1 / fi X (m + 1)
"H" Underflow signal of 8-bit prescaler (Note2) "L"
1 / fi X (m + 1) X n PWM pulse output from TA iOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fi : Frequency of count source (f1, f8, f32, fC32)
Cleared to "0" when interrupt request is accepted, or cleared by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16
Fig. 1.57. Example of how an 8-bit pulse width modulator operates
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Real-time port mode
When Real-time port output is selected, the data previously written to the port Pm latch is clocked into the Real-time port latch each time the corresponding Timer Ai underflows. The Real-time port data is written to the corresponding port Pm register. When the Real-time port mode select bit changes state from "0" to "1", the value of the Real-time port latch becomes "0", which is ouput from the corresponding pin. It is when Timer Ai underflows first that the Real-time port data is ouput. If the Real-time port data is modified when the Real-time port function is enabled, the modified value is output when Timer Ai underflows next time. The port functions as an ordinary port when the Real-time port function is disabled. Make sure Timer Ai for Real-time port output is set for timer mode, and is set to have "no gate function" using the gate function select bit. Also, before setting the Real-time port mode select bit to "1", temporarily turn off Timer Ai and write its set value to the register. Figure 1.58 shows the block diagram for Real-time port output. Figure 1.59 shows the Real-time control register. Figure 1.60 shows timing in Real-time port output operation.
TQ Data bus Port latch D
P30/RTP00
RTP0 Real-time port select bit
TQ f1 fS f32 fC132 Timer Bj overflow Timer Ak overflow * Timer mode Data bus Timer Ai interrupt Data bus Port latch D
P31/RTP01
TAiiN
2
Noise filter
Timer Ai
~ ~
~ ~
Timer Ai+1 overflow Data bus
TQ Port latch D RTP7 Real-time port select bit
P46/RTP70
j=2, k=4, 0, m=0, 1 when i=0, 1
Set values for Real-time port used in Timer Ai mode register
Timer Ai mode register (Address 039616 and 039716)
b7 b6 b5 b4 b3 b2 b1 b0
TQ Data bus Port latch D
P47/RTP71
0
0
0
0
Real time port latch
Fig. 1.58. Block diagram of Real-time port output
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer A
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Real-time port control register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RTP
Address 03FF16
When reset XXXX00002
Bit symbol
RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7
Bit name
Function
RW
P30, P31 real-time port mode select bit P32, P33 real-time port mode select bit P34, P35 real-time port mode select bit P36, P37 real-time port mode select bit P40, P41 real-time port mode select bit P42, P43 real-time port mode select bit P44, P45 real-time port mode select bit P46, P47 real-time port mode select bit
The corresponding ports of output is controlled 0 : Ordinary port output 1 : Real-time port output OO
OO
OO OO
Note: The corresponding port direction register is invalid
Figure 1.59. Real-time port control register
Underflow
Counter content (hex)
Underflow
Start count
"1" Timer Ai. Count start flag "0" Timer Ai interrupt request bit (i=0, 1, 5, 6) Real time port output 5516 AA16 "1" "0"
Writing to port Pm register (m=0, 1, 2, 12) Value to port Pm (example) 5516 AA16
Note : After a reset, the value of the real time port latch is "00". The value of the real time port latch changes irrespective of the real time port mode select bit as the value of the port Pm register is updated by an underflow of the corresponding timer
Figure 1.60. Timing in Real-time port output operation
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 1.61shows the block diagram of Timer B. Figures 1.62 and 1.63 show the Timer B-related registers. Use the Timer Bi mode register (i= 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: *Timer mode: The timer counts an internal count source. *Event counter mode: The timer counts pulses from an external source or a timer overlfow. *Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits Data bus low-order bits Low-order 8 bits
Clock source selection
f1 f8 f32 fC32
TBiIN (i = 0 to 5)
High-order 8-bits
* Timer * Pulse period/pulse width measurement
Reload register (16)
* Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow j = i - 1. Note, however, j = 2 when i = 0 j = 5 when i = 3 TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Counter (16)
Address 039116 039016 0393 16 0392 16 039516 039416 035116 035016 035316 035216 035516 035416
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Fig. 1.61. Block diagram of Timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited
R
W
Operation mode select bit
MR0 MR1 MR2 Function varies with each operation mode
(Note 1)
(Note 2)
MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode)
Note 1: Timer B0, Timer B3. Note 2: Timer B1, Timer B2, Timer B4, Timer B5.
Fig. 1.62. Timer B-related registers (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 TB3 TB4 TB5
Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function
* Timer mode Counts the timer's period * Event counter mode Counts external pulses input or a timer overflow * Pulse period / pulse width measurement mode Measures a pulse period or width
RW
000016 to FFFF16
000016 to FFFF16
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Timer B3, 4, 5 count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBSR
Address 034016
When reset 000XXXXX 2
Bit symbol
Bit name
Function
RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0".
TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0".
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Fig. 1.63. Timer B-related registers (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.30). Figure 1.64 shows the Timer Bi mode register in timer mode. Usage Precaution
Reading the Timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the Timer Bi register with the reload timing gets "FFFF16". Reading the Timer Bi register after setting a value in the Timer Bi register with a count halted but before the counter starts counting gets a proper value. Table 1.30. Timer mode specifications
Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer f1, f8, f32, fc32 Count down When the timer underflows, it reloads the reload register contents before continuous counting 1/(n+1) n: Set value Specification
Count start flag is set (=1) Count start is reset (=0) When the timer underflows Programmable I/O port or gate input Count value can be read out by reading Timer Bi register When counting stopped When a value is written to Timer Bi register, it is written to both reload register and counter When the timer underflows, it reloads the reload register contents before continuous counting When a value is written to Timer Bi register,it is written to only reload register (Transferred to counter at next reload time)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1
Bit name
b1 b0
Function
0 0 : Timer mode
R
W
Operation mode select bit Invalid in timer mode Can be "0" or "1"
0 (Fixed to "0" in timer mode ; i = 0, 3) MR2
(Note 1)
Nothing is assigned (i=1, 2, 4, 5) Write "0" when writing to this bit. If read, the value is indeterminate. (Note 2)
Invalid in timer mode. MR3
Write "0" when writing to this bit. If read in timer mode, the value is indeterminate.
b7 b6
TCK0 TCK1
Count source select bit
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Timer B0, Timer B3. Note 2: Timer B1, Timer B2, Timer B4, Timer B5.
Fig. 1.64. Timer Bi mode register in timer mode
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.31). Figure 1.65. shows the Timer Bi mode register in event counter mode. Usage Precaution
Reading the Timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the Timer Bi register with the reload timing gets "FFFF16". Reading the Timer Bi register after setting a value in the Timer Bi register with a count halted but before the counter starts counting gets a proper value
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.31. Timer specifications in event counter mode
Item Count source * * * * Specification External signals input to TBiIN pin Effective edge of count source can be a rising edge or falling edge or both as selected by software Count down When the timer underflows, it reloads the reload register content before continous counting. n: Set value
Count operation
Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer
1/(n + 1) Count start flag is set (=i) Count start flag is reset (=0) The timer underflows. Count source input
Count value can be read out by reading Timer Bi register * When counting stops When a value is written to Timer Bi register, it is written to both reload register and counter. When counting is in progress When a value is written to Timer Bi register, it is written to only reload register. (Transferred to counter at next reload time).
*
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
b1 b0
Function
0 1 : Event counter mode
b3 b2
R
W
Operation mode select bit
Count polarity select bit (Note 1) MR1
0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited
(Note 2)
0 (Fixed to "0" in event counter mode; i = 0, 3) MR2 Nothing is assigned (i = 1, 2, 4, 5). Write "0" when writing to this bit. If read, the value is indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write "0". If read, the value in event counter mode, is indeterminate. Invalid in event counter mode. Can be "0" or "1". 0 : Input from TBi IN pin (Note 4) 1 : TBj overflow
(j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3)
(Note 3)
MR3
TCK0
TCK1
Event clock select
Note 1: Valid only when input from the TBi IN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, Timer B3. Note 3: Timer B1, Timer B2, Timer B4, Timer B5. Note 4: Set the corresponding port direction register to "0".
Fig. 1.65. Timer Bi mode register in event counter mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.32). Figure 1.66 shows the Timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.67 shows the operation timing when measuring a pulse period. Figure 1.68 shows the operation timing when measuring a pulse width. Usage Precautions
(1) If changing the measurement mode select bit is set after a count is started, the Timer Bi interrupt request bit goes to "1". (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, Timer Bi interrupt request is not generated. Table 1.32. Timer specifications in pulse period/pulse width measurement mode
Item Count source Count operation f1, f8, f32, fc32 Count up Counter value 000016 is transferred to reload register at measurement pulse s effective edge and the timer continues counting. Count start flag is set (=1) Count start flag is reset (=0) When measurement pulse s effective edge is input (Note 1) When an overflow occurs. (Simultaneously, the Timer Bi overflow flag changes to 1 . The timer Bi overlfow changes to 0 when the count start flag is 1 and the value is written to another Timer Bi timer mode register). Measurement pulse input When Timer Bi register is read, it indicates the reload register s content (measurement result) (Note 2) Cannot write to timer Specification
Count start condition Count stop condition Interrupt request generation timing
TBiIN pin function Read from timer Write to timer
Note 1: An interrupt requst is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the Timer Bi register is indeterminate until the second effective edge is input.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol TBiMR(i=0 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
1 0 : Pulse period / pulse width measurement mode
b3 b2
R
W
MR0 Measurement mode select bit MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited
0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3) MR2 Nothing is assigned. ( i= 1, 2, 4, 5) Write "0" when writing to this bit. If read, the value is indeterminate. Timer Bi overflow flag ( Note 1) Count source select bit TCK1 0 : Timer did not overflow 1 : Timer has overflowed
b7 b6
(Note 2)
(Note 3)
MR3 TCK0
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: The Timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the Timer Bi mode register. This flag cannot be set to "1" by software. Note 2: Timer B0, Timer B3. Note 3: Timer B1, Timer B2, Timer B4, Timer B5.
Fig. 1.66. Timer Bi mode register in pulse period/pulse width measurement mode
Count source
Measurement pulse
"H" "L" Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches "0000 16" Count start flag
"1" "0"
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Fig. 1.67. Operation timing when measuring a pulse period
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer B
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Count source
Measurement pulse
"H" "L"
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches "000016"
"1" "0"
Count start flag
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Fig. 1.68. Operation timing when measuring a pulse width
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer functions for three-phase motor control
Use of more than one built-in Timer A and Timer B provides the means of outputting three-phase motor driving waveforms. Figures 1.69 to 1.71 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
034816
When reset
0016
Bit symbol
INV00
Bit name
Description
R
W
Effective interrupt output 0: A Timer B2 interrupt occurs when the timer polarity select bit A1 reload control signal is "1". (Note 4) 1: A Timer B2 interrupt occurs when the timer A1 reload control signal is "0". Effective only in three-phase mode 1 Effective interrupt output 0: Not specified. specification bit 1: Selected by the effective interrupt output (Note4) polarity selection bit. Effective only in three-phase mode 1 Mode select bit (Note 2) Output control bit Positive and negative phases concurrent L output disable function enable bit Positive and negative phases concurrent L output detect flag Modulation mode select bit (Note 3) Software trigger bit 0: Normal mode 1: Three-phase PWM output mode 0: Output disabled 1: Output enabled 0: Feature disabled 1: Feature enabled
INV01
INV02 INV03
INV04
INV05 INV06 INV07
0: Not detected yet 1: Already detected 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode 1: Trigger generated The value, when read, is "0".
(Note 1)
Note 1: No value other than "0" can be written. Note 2: Selecting three-phase PWM output mode causes P8 0, P81, and P72 through P75 to output U, U, V, V, W, and W, and works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for setting Timer B2 interrupt frequency. Note 3: In triangular wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of Timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of Timer A output and with the transfer trigger signal The data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. Note 4: To write "1" both to bit 0 (INV00) and bit 1 (INV01) of the three-phase PWM control register, set in advance the content of the Timer B2 interrupt occurrences frequency set counter.
Three-phase 0
PWM control register 1
Symbol
INVC1
b7 b6 b5 b4 b3 b2 b1 b0
Address
034916
When reset
0016
Bit symbol
INV10
Bit name
Timer Ai start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Short circuit timer count source select bit
Description
0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 0: Three-phase mode 0 1: Three-phase mode 1 0 : Not to be used 1 : f1/2
R
W
INV11 INV12
Nothing is assigned. Write "0" when writing to this bit. If read, the value is "0".
Reserved bit Always set to "0"
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0".
Note 1: To use three-phase PWM output mode, write "1" to INV12.
Fig. 1.69. Registers related to timers for three-phase motor control
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions For Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase output buffer register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IDB0
Bit Symbol
Address 034A16
When reset 3F16
Bit name
U phase output buffer 0 U phase output buffer 0 V phase output buffer 0 V phase output buffer 0 W phase output buffer 0 W phase output buffer 0
Function
Setting in U phase output buffer 0 Setting in U phase output buffer 0 Setting in V phase output buffer 0 Setting in V phase output buffer 0 Setting in W phase output buffer 0 Setting in W phase output buffer 0
R
W
DU0 DUB0 DV0 DVB0 DW0 DWB0
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0".
Note: When executing read instruction of this register, the contents of three-phase shift register is read out.
Three-phase output buffer register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IDB1
Bit Symbol
Address 034B16
When reset 3F16
Bit name
U phase output buffer 1 U phase output buffer 1 V phase output buffer 1 V phase output buffer 1 W phase output buffer 1 W phase output buffer 1
Function
Setting in U phase output buffer 1 Setting in U phase output buffer 1 Setting in V phase output buffer 1 Setting in V phase output buffer 1 Setting in W phase output buffer 1 Setting in W phase output buffer 1
R
W
DU1 DUB1 DV1 DVB1 DW1 DWB1
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0".
Note: When executing read instruction of this register, the contents of three-phase shift register is read out.
Dead time timer
b7 b0
Symbol DTT
Address 034C16
When reset Indeterminate
Function
Set dead time timer
Values that can be set
1 to 255
R
W
Timer B2 interrupt occurrences frequency set counter
b3 b0
Symbol ICTB2
Address 034D16
When reset Indeterminate
Function
Set occurrence frequency of Timer B2 interrupt request
Values that can be set
1 to 15
R
W
Note1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of threephase PWM control register 0, do not change the B2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. Note 2: Do not write at the timing of an overflow occurrence in Timer B2
Fig. 1.70. Registers related to timers for three-phase motor control
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TA1 TA2 TA4 TB2 Function
Address 038916,038816 038B16,038A16 038F16,038E16 039516,039416
When reset Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
RW
* Timer mode Counts an internal count source * One-shot timer mode Counts a one shot width
000016 to FFFF16 000016 to FFFF16
Note: Read and write data in 16-bit units.
Timer Ai-1 register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TA11 TA21 TA41 Function
Address 034316,034216 034516,034416 034716,034616
When reset Indeterminate Indeterminate Indeterminate
Values that can be set
RW
Counts an internal count source
000016 to FFFF16
Note: Read and write data in 16-bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR Bit symbol
TA1TGL
Address 038316 Bit name Timer A1 event/trigger select bit
When reset 0016 Function
b1 b0
RW
TA1TGH TA2TGL
0 0 : Input on TA1 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected
b3 b2
Timer A2 event/trigger select bit
TA2TGH TA3TGL TA3TGH
0 0 : Input on TA2 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected
b5 b4
Timer A3 event/trigger select bit
0 0 : Input on TA3 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger select bit
0 0 : Input on TA4 IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Address 038016 Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
When reset 0016 Function 0 : Stops counting 1 : Starts counting RW
Fig. 1.71. Registers related to timers for three-phase motor control
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions For Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase motor driving waveform output mode (three-phase waveform mode)
Setting "1" in the mode select bit (bit 2 at 034816) shown in Figure 1.69, causes three-phase waveform mode that uses four Timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.72, set Timers A1, A2, and A4 in one-shot timer mode, set the trigger in Timer B2, and setTimer B2 in timer mode using the respective timer mode registers.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
10
Symbol TA1MR TA2MR TA3MR TMOD0 TMOD1 MR0
Address 039716 039816 039A16 Bit name Operation mode select bit Pulse output function select bit External trigger select bit Trigger select bit
When reset 0016 0016 0016 Function
b1 b0
Bit symbol
RW
1 0 : One-shot timer mode 0 (Must always be "0" in three-phase PWM output mode) Invalid in three-phase PWM output mode 1 : Selected by event/trigger select register
MR1 MR2 MR3 TCK0 TCK1
0 (Must always be "0" in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Timer B2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TB2MR Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0
Address 039D16
When reset 00XX00002
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
RW
Invalid in timer mode Can be "0" or "1" 0 (Fixed to "0" in timer mode ; i = 0) Invalid in timer mode.
b7 b6
Count source select bit TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Fig. 1.72. Timer mode registers in three-phase waveform mode
1-96
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.73 shows the block diagram for three-phase waveform mode. In three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 as active on the "L" level. Of the timers used in this mode, Timer A4 controls the U phase and U phase, timer A1 controls the V phase and V phase, and Timer A2 controls the W phase and W phase respectively; Timer B2 controls the periods of one-shot pulse output from Timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the "L" level of the positive waveform output (U phase, V phase, and W phase) not to lap over the "L" level of the negative waveform output (U phase, V phase, and W phase). To set the dead time, use three 8-bit timers sharing the reload register. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the timer (034C16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 034916). The timer can receive another trigger again before the count from the previous trigger is completed. In this instance, the timer reloads the reload register's contents aand starts the down count again. Because the timer for setting dead time works as a one-shot timer, it starts outputting pulses if triggered; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger. The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V phase, and W phase) in three-phase waveform mode are output from respective ports by means of setting "1" in the output control bit (bit 3 at 034816). Setting "0" in this bit causes the ports to return to a general purpose I/O port. This bit can be set to "0" by use of the applicable instruction, entering a falling edge in the NMI terminal, or by resetting. Also, if "1" is set in the positive and negative phases concurrently, the L output disable function enable bit (bit 4 at 034816) causes one of the pairs of U phase and U phase, V phase and V phase, and W phase and W phase to go to "L". As a result, the port becomes the state set by the port direction register.
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INV00 1 R Interrupt request bit INV05 0 INV07 f1 INV04 1/2 1 Trigger Trigger Dead time timer setting n = 1 to 255 Bit 0 at 034B16 Bit 0 at 034A16 DQ T INV06 U phase output control circuit DU1 DU0 U phase output signal INV12 (Note) Reload register n = 1 to 255 RESET NMI Interrupt occurrence frequency set counter n = 1 to 15
INV01 INV11 INV03 D Q
Circuit foriInterrupt occurrence frequency set counter
Overflow
Timer B2
Signal to be written to B2 INV10
(Timer mode)
U(P80)
Trigger signal for timer Ai start
Control signal for timer A4 reload
Timer A4
D T T Q D Q
Reload
Timer A4-1
Trigger signal for transfer Three-phase output shift register (U phase)
Trigger
Timer A4 counter DUB1 U phase output signal DUB0
(One-shot timer mode) TQ
D T T Q D Q
Rev. G Timer Functions For Three-phase Motor Control
INV11 DQ T
U(P81)
Specifications in this manual are tentative and subject to change
Fig. 1.73. Block diagram for three-phase waveform mode
Trigger Trigger Dead time timer setting (8) n = 1 to 255 V phase output signal V phase output signal Reload INV06 Timer A1-1 DQ T
1-98
V phase output control circuit TQ Trigger Trigger Reload Timer A2-1 INV06 U phase output control circuit INV11 For short circuit prevention Dead time timer setting (8) n = 1 to 255 W phase output signal W phase output signal
To be set to "0" when timer A4 stops
V(P72)
Timer A1
Trigger
Timer A1 counter
V(P73)
DQ T
(One-shot timer mode)
To be set to "0" when timer A1 stops
W(P74)
DQ T
Timer A2
Trigger
Timer A2 counter
DQ T
W(P75)
(One-shot timer mode) INV11 TQ
MITSUBISHI MICROCOMPUTERS
M30222 Group
To be set to "0" when Timer A2 stops
Diagram for switching to P8 0, P81, and to P72 - P75 is not shown.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Note: To use three-phase output mode, write "1" to INV12
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Delta modulation
To generate a PWM waveform of triangular wave modulation, set "0" in the modulation mode select bit (bit 6 at 034816). Also, set "1" in the Timers A4-1, A1-1, A2-1 control bit (bit 1 at 034916). In this mode, each of Timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register's content to the counter every time Timer B2 counter's content becomes 000016. If "1" is set to the effective interrupt output specification bit (bit 1 at 034816), the frequency of interrupt requests that occur every time the Timer B2 counter's value becomes 000016 can be set by use of the Timer B2 counter (034D16) . The frequency of occurrences is dependent on the reload value of Timer B2. The reload value cannot be "0". Setting "1" in the effective interrupt output specification bit (bit 1 at 034816) provides the means to choose which value of the Timer A1 reload control signal to use, "0" or "1", to cause Timer B2's interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 034816). An example of U phase waveform is shown in Figure 1.74, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 034A16). And set "0" in DUB0 (bit 1 at 034A16). In addition, set "0" in DU1 (bit 0 at 034B16) and set "1" in DUB1 (bit 1 at 034B16). Also, set "0" in the effective interrupt output specification bit (bit 1 at 034816) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a Timer B2 interrupt occurs when the Timer B2 counter's content becomes 000016 as many as (setting) times. Furthermore, set "1" in the effective interrupt output specification bit (bit 1 at 034816), set in the effective interrupt polarity select bit (bit 0 at 034816) and set "1" in the interrupt occurrence frequency set counter (034D16). These settings cause a Timer B2 interrupt to occur every other interval when the U phase output goes to "H". When the Timer B2 counter's content becomes 000016, Timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 034B16) and that of DU0 (bit 0 at 034A16) are set in the threephase output shift register (U phase), the content of DUB1 (bit 1 at 034B16) and that of DUB0 (bit 1 at 034A16) are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the Timer B2 counter's content becomes 000016. The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the Timer A4 counter counts the value written to Timer A4 (038F16, 038E16) and when Timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the "L" level of the U phase waveform does not lap over the "L" level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0" by the effect of the one-shot pulses. When the timer for setting dead time
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions For Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the Timer B2 counter's content becomes 000016, the Timer A4 counter starts counting the value written to Timer A4-1 (034716, 034616), and starts outputting one-shot pulses. When Timer A4 finishes outputting one-shot pulses, the threephase shift register's content is shifted one position, but if the three-phase output shift register's content changes from "0" to "1" as a result of the shift, the output level changes from "L" to "H" without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the values of Timer B2, Timer A4, and Timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform.
A carrier wave of triangular waveform
Carrier wave Signal wave
Timer B2 Timer B2 interrupt occurs Rewriting Timer A4 and Timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit
Trigger signal for Timer Ai start (Timer B2 overflow signal) Timer A4 output
m
n
m
n
m
p
o
Control signal for Timer A4 reload U phase output signal U phase output signal U phase U phase
The Three-phase shift register shifts in synchronization with the falling edge of the A4 output.
Dead time Note: Set to Triangular wave modulation mode and to Three-phase mode 1.
Fig. 1.74. Timing chart operation (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Assigning certain values to DU0 (bit 0 at 034A16) and DUB0 (bit 1 at 034A16), and to DU1 (bit 0 at 034B16) and DUB1 (bit 1 at 034B16) allows the user to output the waveforms as shown in Figure 1.75, that is, to output the U phase alone, to fix U phase to "H", to fix the U phase to "H," or to output the U phase alone.
A carrier wave of triangular waveform
Carrier wave Signal wave
Timer B2
Rewriting Timer A4 every Timer B2 interrupt occurres. Timer B2 interrupt occurres. Rewriting three-phase buffer register.
Trigger signal for timer Ai start (Timer B2 overflow signal) Timer A4 output
m n
m
n
m
p
o
Control signal for Tmer A4 reload U phase output signal U phase output signal U phase U phase
Dead time Note: Set to triangular wave modulation mode and to three-phase mode 0.
Fig. 1.75. Timing chart of operation (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions For Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set "1" in the modulation mode select bit (bit 6 at 034816). Also, set "0" in the Timers A4-1, A1-1, and A2-1 control bit (bit 1 at 034916). In this mode, the timer registers of Timers A4, A1, and A2 comprise conventional Timers A4, A1, and A2 alone, and reload the corresponding timer register's content to the counter every time the Timer B2 counter's content becomes 000016. The effective interrupt output specification bit (bit 1 at 034816) and the effective interrupt output polarity select bit (bit 0 at 034816) go nullified. An example of U phase waveform is shown in Figure 1.76, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 034A16), and set "0" in DUB0 (bit 1 at 034A16). In addition, set "0" in DU1 (bit 0 at 034A16) and set "1" in DUB1 (bit 1 at 034A16). When the Timer B2 counter's content becomes 000016, Timer B2 generates an interrupt, and Timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the threephase buffer register's content is set in the three-phase shift register every time the Timer B2 counter's content becomes 000016. The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to Timer A4 (038F16, 038E16) and when Timer A4 finishes outputting one-shot pulses, the three-phase output shift register's content is shifted one position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the "L" level of the U phase waveform doesn't lap over the "L" level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0 "by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the Timer B2 counter's content becomes 000016, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of DUB1 and DUB0 are set in the three-phase shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the threephase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the values of Timer B2 and Timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform. Setting "1" both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to "H" as shown in Figure 1.77.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions for Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A carrier wave of sawtooth waveform
Carrier wave Signal wave
Timer B2
Trigger signal for Timer Ai start (Timer B2 overflow signal)
Interrupt occurres. Rewriting the value of Timer A4.
Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the Timer B overflow.
Timer A4 output
m
n
o
p
U phase output signal U phase output signal U phase
The three-phase shift register shifts in synchronization with the falling edge of Timer A4.
U phase
Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0.
Fig. 1.76. Timing chart of operation (3)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Timer Functions For Three-phase Motor Control
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A carrier wave of sawtooth waveform
Carrier wave Signal wave
Timer B2
Interrupt occurres. Rewriting the value of Timer A4.
Interrupt occurres. Rewriting the value of Timer A4.
Trigger signal for Timer Ai start (Timer B2 overflow signal)
Rewriting three-phase output buffer register
Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the Timer B overflow.
Timer A4 output
m
n
p
The three-phase shift register shifts in synchronization with the falling edge of Timer A4.
U phase output signal U phase output signal U phase U phase
Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0.
Fig. 1.77. Timing chart of operation (4)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial Communications
The five channels of serial communication that are available are: UART0, UART1, UART2, SI/O3 and SI/O4.
UART0 to 2
UART0, UART1 and UART2 have exclusive timers to generate the transfer clock, so each operates independently from the others. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2 is compliant with the Subscriber Identity Module (SIM) interface with some extra settings added in clock-asynchronous serial I/O mode. It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. UART2 also provides support for both I2C and SPI transfer formats. Figure 1.78 shows the block diagram of UART0, UART1 and UART2. Figures 1.79 and 1.80 show the block diagram of the transmit/receive unit. Figures 1.81 to 1.86 show the registers related to UARTi. Table 1.33 shows the comparison of functions of UART0 through UART2.
Table 1.33. Comparison of functions of UART0 through UART2
Function CLK polarity selection LSB first/MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Separate CTS/RTS pins Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection I2C SPI UART0 Supported (Note 1) Supported (Note 1) Supported (Note 1) Not supported Supported Not supported Supported (Note 3) Not supported CMOS or N-channel open drain Not supported Not supported Not supported Not supported UART1 Supported (Note 1) Supported (Note 1) Supported (Note 1) Supported (Note 1) Not supported Not supported Supported (Note 3) Not supported CMOS or N-channel open drain Not supported Not supported Not supported Not supported UART2 Supported (Note 1) Supported (Note 2) Supported (Note 1) Not supported Not supported Supported (Note 4) Not supported Supported N-channel open drain output (Note 5) Supported (Note 4) Supported Supported Supported
Note 1: Only in Clock Synchronous Serial I/O mode. Note 2: Only in Clock Synchronous Serial I/O mode and 8-bit UART mode. Note 3: Only in UART mode. Note 4: Using SIM interface. Note 5: Input and output when using SIM interface for UART2 only.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART0)
RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A116)
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type (when internal clock is selected)
CLK0
CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected
Clock synchronous type (when external clock is selected)
CTS0 / RTS0
Vcc CTS/RTS disabled CTS/RTS separated CTS0 from UART1
RTS0
CTS0
(UART1)
RxD1
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A916)
1/16
TxD1
UART reception Reception control circuit Receive clock Transmit/ receive unit
Clock synchronous type UART transmission
1/16
1 / (n1+1)
External
Clock synchronous type Clock synchronous type
1/2 (when internal clock is selected)
Transmission control circuit
Transmit clock
receive Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected)
CLK1 CTS1 / RTS1 / CTS0 / CLKS1
CLK polarity reversing circuit
CTS/RTS disabled CTS/RTS separated Clock output pin select switch VCC CTS/RTS disabled CTS0
RTS1
CTS1
CTS0 to UART0 TxD polarity reversing circuit Transmit/ unit Transmission control circuit Transmit clock
(UART2)
RxD2
RxD polarity reversing circuit
1/16
TxD2
UART reception
Clock source selection f1 f8 f32 Internal Bit rate generator (address 037916)
Clock synchronous type UART transmission
1/16
Reception control circuit
Receive clock
1 / (n2+1)
External
Clock synchronous type Clock synchronous type
1/2
(when internal clock is selected)
CLK2
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS selected
CTS/RTS disabled
CTS2 / RTS2
Vcc CTS/RTS disabled
RTS2
CTS2
n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2)
Fig. 1.78. Block diagram of UARTi (i= 0 to 2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous type UART (7 bits) UART (8 bits)
1SP
PAR disabled
Clock synchronous type
UART (7 bits)
UARTi receive register
RxDi
SP 2SP
SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16
MSB/LSB conversion circuit
Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16
UART (8 bits) UART (9 bits)
UART (9 bits)
Clock synchronous type
2SP SP SP 1SP
PAR
PAR enabled
UART
TxDi
PAR disabled Clock synchronous type
UART (7 bits)
UART (7 bits) UART (8 bits) Clock synchronous type
UARTi transmit register
"0"
SP: Stop bit PAR: Parity bit
Fig. 1.79. Block diagram of UARTi (i = 0,1) transmit/receive unit
No reverse
RxD2
RxD data reverse circuit
Reverse
Clock synchronous type
1SP SP 2SP SP
PAR
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
UART2 receive register
PAR enabled
UART
UART (9 bits)
Clock synchronous type
PAR: Parity bit
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 receive buffer register Address 037E16 Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit buffer register Address 037A16 Address 037B16
UART (8 bits) UART (9 bits)
PAR enabled
UART (9 bits) UART
Clock synchronous type
2SP SP SP 1SP
PAR
PAR disabled
Clock synchronous type
"0"
UART (7 bits) UART (8 bits)
Clock synchronous type
UART(7 bits)
UART2 transmit register
Error signal output disable
No reverse
Error signal output circuit
Error signal output enable Reverse
TxD data reverse circuit
TxD2
SP: Stop bit PAR: Parity bit
Fig. 1.80. Block diagram of UART2 transmit/receive unit
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16
When reset Indeterminate Indeterminate Indeterminate Function RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
O
Bit symbol
Symbol U0RB U1RB U2RB
Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16
When reset Indeterminate Indeterminate Indeterminate
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Function (During UART mode) Receive data
RW
Nothing is assigned. Write "0" when writing to this bit. If read, the value is "0".
MDFLT SPI Mode fault flag (Note 3) 0 : Not detected 1 : Detected
Invalid
Invalid
OO
ABT OER FER PER SUM
Arbitration lost detecting flag (Note 2)
0 : Not detected 1 : Detected
Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid
0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A6 16, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and only "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value of this bit is "0". Note 3: Mode fault flag is allocated to U2RB only. Nothing is assigned in bit 10 of U0RB and U1RB. The bit is read only. After MDFLT is set, it can be reset only by exiting SPI mdoe.
UARTi bit rate generator
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n+1
Fig. 1.81. Serial I/O related register (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address When reset 0016 03A016, 03A816
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
0 : Internal clock 1 : External clock Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be "0"
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
Serial I/O mode select bit
0 0 0 : Serial I/O invalid 0 0 1 : SPI mode (Note) 0 1 0 : I 2C mode (Note) 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock Invalid
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited Must always be "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to "0"
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
Odd/even parity select bit Invalid
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity reverse bit
Invalid 0 : No reverse 1 : Reverse Usually set to "0"
Note: Bit 2 to bit 0 are set to "010 2" when I 2C or SPI mode are used.
Fig. 1.82. Serial I/O related registers (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC0(i=0,1)
Address 03A416, 03AC16
When reset 0816
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
CTS/RTS function select bit Transmit register empty flag
TXEPT
0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
CRD
CTS/RTS disable bit
NCH
Data output select bit
CKPOL
CLK polarity select bit
Must always be "0"
UFORM Transfer format select bit 0 : LSB first 1 : MSB first
Must always be "0"
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
(Note 3)
Symbol U2C0
Address 037C16
When reset 0816 Function (During clock synchronous serial I/O mode)
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
Function (During UART mode)
b1 b0
RW
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port)
CTS/RTS function select bit Transmit register empty flag
TXEPT
0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port)
CRD
CTS/RTS disable bit
Nothing is assigned. Write "0" when writing to this bit. If read, the value is "0".
CKPOL CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge For SPI, clock is high between transfers 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge For SPI, clock is low between transfers
Must always be "0"
UFORM Transfer format select bit 0 : LSB first 1 : MSB first
0 : LSB first 1 : MSB first
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8 bit UART mode are valid.
Fig. 1.83. Serial I/O-related registers (3)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit Receive complete flag
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to "0"
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Invalid
RW
RE RI
Receive enable bit Receive complete flag
U2IRS
UART2 transmit interrupt cause select bit
U2RRM UART2 continuous receive mode enable bit
U2LCH Data logic select bit U2ERE Error signal output enable bit
0 : No reverse 1 : Reverse 0 : Output disabled
1 : Output enabled
Fig. 1.84. Serial I/O-related registers (4)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
When reset X00000002
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
U1IRS
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK1 only)
Invalid
U1RRM UART1 continuous receive mode enable bit
Invalid
CLKMD0 CLK/CLKS select bit 0
Invalid
CLKMD1 CLK/CLKS select bit 1 (Note)
Must always be "0"
1 : Transfer clock output from multiple pins function selected RCSP Separate CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated 0 : CTS/RTS shared pin 1 : CTS/RTS separated
Nothing is assigned. Write "0" when writing to this bit. If read, the value is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A8 16) = "0".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR
Address 037716
When reset 0016
Bit symbol IICM ABC BBS LSYN
Bit name I2C mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I 2 C mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
Function (During UART mode) Must always be "0" Must always be "0" Must always be "0"
RW
(Note 1)
0 : Disabled 1 : Enabled Must always be "0"
Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2
Must always be "0"
ABSCS
ACSE
Must always be "0"
SSS
Must always be "0" 0 : Analog delay output is selected 1 : Digital delay output is selected (Must always be "0" when not using I2C mode)
SDDS
SDA digital delay select bit (Note 2, 3)
Note 1: Nothing but "0" may be written. Note 2: When not in I 2C mode, do not set this bit by writing a "1". during normal mode, fix it to "0". When this
bit - "0" , UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS = "0", do not read or write to U2SMR3 register. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected only the digital delay value is effective.
Fig. 1.85. Serial I/O-related registers (5)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Serial Communications
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR2
Address 037616
When reset 0016
Bit symbol IICM2 CSC SWC ASL STAC SWC2 SDHI SHTC
Bit name I2 C mode selection bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit Refer to Table 1.44 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output
Function
RW
0: Enabled 1: Disabled (high impedance) Set this bit to "1" in I 2C mode
UART2 Special mode register 3 (I2C and SPI bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR3 Bit symbol SPIM CPHA Bit name
Address 037516
When reset 0016
SPI mode select bit SPI clock-phase select bit
Function during clock synchronous serial I/O mode 0 : Normal mode 1 : SPI mode 0 : Data latched on falling clock edge 1 : Data latched on rising clock edge
Function during UART mode
Must always be "0'
RW
Must always be "0'
Nothing is assigned. Write "0" when writing to these bits. If read, the value is Indeterminate. However, when SDDS = "1", a "0" value is read. (Note 1)
DL0
__
SDA digital delay set up bit (Notes 1, 2, 3, 4, 5)
b7 b6 b5
DL1
DL2
Note 1:
000: 001: 010: 011: 100: 101: 110: 111:
Analog delay is selected 2 cycle of 1/f(X IN) 3 cycle of 1/f(X IN) 4 cycle of 1/f(X IN) 5 cycle of 1/f(X IN) 6 cycle of 1/f(X IN) 7 cycle of 1/f(X IN) 8 cycle of 1/f(X IN)
Digital delay is selected
Note 2:
Note 3: Note 4: Note 5:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3 (U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to; when read, the value is indeterminate. These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate. When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 100ns. Be sure to take this into account when using this device. Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
Fig. 1.86. Serial I/O-related registers (6)
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.34 and 1.35 list the specifications of the clock synchronous serial I/O mode. Figure 1.87 shows the UARTi transmit/receive mode register.
Table 1.34. Specifications of clock synchrounous serial I/O mode (1)
Item Transfer data format Transfer clock Transfer data length: 8 bits When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = 0 ): fi/ 2 (n+1) (Note 1) fi = f1, f8, f32 When external clock is selected (bit 3 at addresses 03A016, 03A816 037816 = 1 ): Input from CLKi pin CTS function/RTS function/CTS, RTS function chosen to be invalid To start transmission, the following requirements must be met: -Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = 1 -Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = 0 -When CTS function selected, CTS input level = L If external clock is selected, the following requirements must also me be: -CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16,) = 0 : CLKi input level = H -CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 1 : CLKi input level = L To start reception, the following requirement must be met: -Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = 1 -Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = 1 -Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = 0 If external clock is selected, the following requirements must also be met: -CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 0 : CLKi input level = H -CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 1 : CLKi input level = L When transmitting: -Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = 0 : Interrupts requested when data transferred from UARTi transfer buffer register to UARTi transmit register is complete -Transmit interrupt cause select bit (bit 0, 1 at address 03B016, bit 4 at address 037D16) = 1 : Interrupts requested when data transmission from UARTi transfer register is complete When receiving: -Interrupts requested when data transferred from UARTi receive register to UARTi receive buffer register is complete. Overrun error (Note 2) This error occurs when the next data are ready before contents of UARTi receive buffer register are read out Specification
Transmission/ reception control Transmission start condition
Receiving start condition
Interrupt request generation timing
Error detection
Note 1: n denotes the value 00 16 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Also, the UART receive interrupt requst bit is not set to 1 .
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.35. Specifications of clock synchronous serial I/O mode (2)
Item Select function * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set * Separate CTS/RTS pins (UART0) (Note) UART0 CTS and RTS pins each can be assigned to separate pins * Switching serial data logic (UART2) Whether to invert data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity reverse (UART2) This function is inverting TxD port output and RxD port input. All I/O data level are inverted, including start and stop bits.
Note: The transfer clock output from multple pins and the separate CTS/RTS pins functions cannot be selected simultaneously.
Specification
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016, 03A816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode 0 (Must always be "0" in clock synchronous serial I/O mode)
Note: Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL
Address 037816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 1)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse (Note 2) 1 : Reverse
Note 1: Set the corresponding port direction register to "0". Note 2: Usually set to "0".
Fig. 1.87. UARTi transmit/receive mode register in clock synchronous serial I/O mode
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.36 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state). Fig. 1.88 shows a typical transmit/receive timings in clock synchronous serial I/O mode.
Table 1.36. Input/output pin functions
Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE 16, bit 1 at address 03EF 16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A0 16, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A0 16, 03A816, 037816) = "1" Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE 16, bit 2 at address 03EF 16) = "0" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A4 16, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE 16, bit 3 at address 03EF 16) = "0" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A4 16, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) = "1"
TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input
CTSi/RTSi CTS input (P60, P64, P73)
RTS output Programmable I/O port
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of transit timing (when internal clock is selected)
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi
"L"
TCLK
Stopped pulsing because CTS = "H"
Stopped pulsing because transfer enable bit = "0"
CLKi
TxDi Transmit register empty flag (TXEPT)
"1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt "1" request bit (IR) "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f 1, f8, f32) n: value set to BRGi
Example of receive timing (when external clock is selected)
"1" "0" "1" "0" "1" "0" "H"
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
"L"
1 / fEXT
Receive data is taken in
CLKi
RxDi Receive complete "0" flag (Rl) Receive interrupt request bit (IR)
"1" "0" "1"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register to UARTi receive buffer register
D0 D1 D2 D3 D4 D5
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register
Fig. 1.88. Typical transmit/receive timings in clock synchronous serial I/O mode
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Polarity select function
As shown in Figure 1.89, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock.
* When CLK polarity select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK pin level when not transferring data is "H".
* When CLK polarity select bit = "1"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK pin level when not transferring data is "L".
Fig. 1.89. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.90, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
* When transfer format select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
* When transfer format select bit = "1"
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity select bit = "0".
Fig. 1.90. Transfer format
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MITSUBISHI MICROCOMPUTERS
Rev. G Clock Synchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.91). The multiple pins function is valid only when the internal clock is selected for UART1. Note that when this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64) CLK1 (P65) IN CLK IN CLK
Note: This applies when the internal clock is selected and transmission 1 is performed only in clock synchronous serial I/O mode.
Fig. 1.91. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. When the receive buffer register is read, the unit goes to a receive enable state without having to reset dummy data to the transmit buffer.
(e) Separate CTS/RTS pins function (UART0)
Refer to the Clock Asynchronous Serial I/O Mode section (Page 1-124) for setting the I/O pin functions. This function is invalid if the transfer clock output from the multiple pin function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit 6 at address 037D16) = "1", the data are reversed when writing to the transmit buffer register or reading from the receive buffer register. Figure 1.92 shows an example of the serial data logic switch timing function.
*When LSB first
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
TxD2
(reverse)
D0
D1
D2
D3
D4
D5
D6
D7
Fig. 1.92. Serial data logic switch timing
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.37 and 1.38 list the specifications of the UART mode. Figure 1.93 shows the UARTi transmit/receive mode register.
Table 1.37. Specifications of UART Mode (1)
Item Transfer data format Specification * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or none as selected * Stop bit: 1 bit or 2 bits as selected * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 ="1") : fEXT/16(n+1) (Note 1) (Note 2) * CTS function/RTS function/CTS, RTS function chosen to be invalid * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A5 16, 03AD16, 037D16) = "1" - Tr ansmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D 16) = "0" - When CTS function selected, CTS input level = "L" * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A5 16, 03AD16, 037D16) = "1" - Start bit detection * When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed * Overrun error (Note 3) This error occurs when the next character is received before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 00 16 to FF16 that is set to the UARTi bit rate generator. Note 2: f EXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the last or most recent data written to it. Note also that UARTi receive interrupt requst bit is not set to "1"
Transfer clock
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
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MICROCOMPUTERS
Rev. G Clock Asynchronous Serial I/O Mode
Table 1.38. Specifications of UART Mode (2)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Item Select function
Specification * Separate CTS/RTS pins (UART0) UART0 CTS and RTS functions each can be assigned to separate pins * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function inverts logic value of transferring data. Start bit, parity bit and stop bit are not inverted. *TXD, RXD I/O polarity switch This function inverts TXD port output and R XD port input. All I/O data level is are inverted.
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 1 0 1 : : : : Internal clock External clock (Note) One stop bit Two stop bits
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit
Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
PRYE SLEP
Note: Set the corresponding port direction register to "0".
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Must always be fixed to "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
RW
Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note)
PRYE IOPOL
Note: Usually set to "0".
Fig. 1.93. UARTi transmit/receive mode register in UART mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.39lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state). Figures 1.94 and 1.95 show the typical transmit timings in UART mode (UART0, UART1, UART2). Figure 1.96 shows the typical receive timing in UART mode.
Table 1.39. Input/output pin functions in UART mode
Pin name TxDi (P63, P67, P70) RxDi (P62, P66, P71) Function Serial data output Serial data input Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE 16, bit 1 at address 03EF 16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A0 16, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A0 16, 03A816) = "1" Port P61, P65 direction register (bits 1 and 5 at address 03EE 16) = "0" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A4 16, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE 16, bit 3 at address 03EF 16) = "0" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A4 16, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A4 16, 03AC16, 037C16) = "1" Method of selection
CLKi (P61, P65, P72)
Programmable I/O port Transfer clock input CTS input
CTSi/RTSi (P60, P64, P73)
RTS output Programmable I/O port
(When separate CTS/RTS pins function is not selected)
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MICROCOMPUTERS
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of transmit timing when transfer data is 8 bits long (parity enabled, one-stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L".
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR)
"1" "0" "1" "0"
Parity bit
P
Stop bit
SP
Stopped pulsing because transmit enable bit = "0"
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Example of transmit timing when tranfer data is 9 bits long (parity disabled, two-stop bits)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of BRGi count source (f 1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Fig. 1.94. Typical transmit timings in UART mode (UART0, UART1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of transmit timing when tranfer data is 8 bits long (parity enabled, one-stop bit) Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UART2 transmit buffer register
Note
Transferred from UART2 transmit buffer register to UARTi transmit register Start bit Parity bit
P
TxD2
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
"1" Transmit register empty flag (TXEPT) "0"
Transmit interrupt request bit (IR)
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Fig. 1.95. Typical transmit timings in UART mode (UART2)
Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit)
BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L"
....... .......
Stop bit
D0
D1.......D7
Receive data taken in
Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register
Fig. 1.96. Typical receive timing in UART mode
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MICROCOMPUTERS
Rev. G Clock Asynchronous Serial I/O Mode (a) Separate CTS/RTS pins function (UART0)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" inputs/outputs the CTS signal and RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function select bit (bit 2 of address 03A416). (See Fig. 1.97). This function is effective in UART0 only. With this function chosen, the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit 2 of address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16).
Microcomputer
TXD0 (P63) RXD0 (P62) IN OUT
IC
RTS0 (P6 0) CTS0 (P64)
CTS RTS
Note : The user cannot use CTS and RTS at the same time.
Fig. 1.97. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.98 shows the example of timing for switching serial data logic.
Example of timing for switching serial data logic when LSB is first (parity enabled, one-stop bit)
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TxD2
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit P : Even parity SP : Stop bit
Fig. 1.98. Timing for switching serial data logic
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for NORMAL use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.99 shows the example of detection timing of a bus collision (in UART mode).
Transfer clock
"H" "L" "H" "L" "H" "L"
TxD2
ST
SP
RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit
ST
SP
"1" "0" "1" "0"
ST : Start bit SP : Stop bit
Fig. 1.99. Detection timing of a bus collision (in UART mode)
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MICROCOMPUTERS
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.40 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Figure 1.100 shows a typical transmit/receive timing in UART mode (compliant with the SIM interface).
Table 1.40. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item Transfer data format Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 0378 16 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") Transfer clock Transmit/receive control Other settings Transmit start condition * Withtheinternal clock chosen(bit 3of address 037816= "0") : fi / 16(n+ 1) (Note1) : fi=f1, f8, f32 (Do not use external clock) * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") * The sleep mode select function is not available for UART2 * Set transmissioninterrupt factor to "transm issioncompleted"(bit 4 of address 037D16= "1") * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Receive start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request generation timing * When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" levelis output fromthe TXD2pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the last or most recent data written. Note also the UARTi receive interrupt request bit is not set to "1".
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UART2 transmit buffer register Note
Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 1)
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine.
P
SP
The level is detected by the interrupt routine.
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock Receive enable bit (RE)
"1" "0"
Start bit
Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RxD2 TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 1) Receive complete flag (RI) Receive interrupt request bit (IR)
"1" "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Read to receive buffer
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2
Note: Equal in waveform because TxD 2 and RxD2 are connected.
Fig. 1.100. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
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MICROCOMPUTERS
Rev. G Clock Asynchronous Serial I/O Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.101 shows the output timing of the parity error signal.
* LSB first
Transfer clock RxD2 TxD2 Receive complete flag
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
ST : Start bit P : Even Parity SP: Stop bit
Fig. 1.101. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.102 shows the SIM interface format. Figure 1.103 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Transfer clock TxD2 (direct) TxD2 (inverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
P : Even parity ST: Start bit SP: Stop bit
Fig. 1.102. SIM interface format
Microcomputer
SIM card
TxD2 RxD2
Fig. 1.103. Connecting the SIM interface
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 in I2C Mode
The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.104 shows the UART2 special mode register. Setting the I2C mode select bit (bit 1 of U2SMR) to "1" selects I2C mode. Table 1.41 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode.
Table 1.41. Features in I2C mode
Function 1 2 Source for interrupt number 10 (Note 2) Source for interrupt number 15 (Note 2) Normal mode Bus collision detection UART2 transmission UART2 reception Not delayed TxD2 (output) RxD2 (input) CLK2 UART2 reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed SDA (input/output) (Note 3) SCL (input/output) P72 Acknowledgment detection (ACK) 50ns Reading the terminal regardless of the value of the direction register The value set in latch P70 when the port is selected
3 Source for interrupt number 16 (Note 2) 4 UART2 transmission output delay 5 P70 at the time when UART2 is in use 6 P71 at the time when UART2 is in use 7 P72 at the time when UART2 is in use DMA1 factor at the time when 1 1 0 1 is assigned 8 to the DMA request factor selection bits 9 Noise filter width 10 Reading P71 11 Initial value of UART2 output
Note 1: Make the settings given below when I 2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from one source to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR
Address 037716
When reset 0016
Bit symbol IICM ABC BBS LSYN
Bit name IIC mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : IIC mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
Function (During UART mode) Must always be "0" Must always be "0" Must always be "0"
RW
(Note 1)
0 : Disabled 1 : Enabled Must always be "0"
Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2
ABSCS
ACSE
Must always be "0"
SSS
Must always be "0"
SDDS
SDA digital delay select bit (Note 2, 3)
0 : Analog delay output is Must always be "0" selected 1 : Digital delay output is selected (Must always be "0" when not using I2C mode)
Note 1: Nothing but "0" may be written. Note 2: When not in I 2C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this
bit - "0" , UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS = "0", the U2SMR3 register cannot be read or written to. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected only the digital delay value is effective.
UART2 Special mode register 3 (I2C and SPI bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR3 Bit symbol SPIM CPHA Bit name
Address 037516
When reset 0016
SPI mode select bit SPI clock-phase select bit
Function during clock synchronous serial I/O mode 0 : Normal mode 1 : SPI mode 0 : Data latched on falling clock edge 1 : Data latched on rising clock edge
Function during UART mode
Must always be "0'
RW
Must always be "0'
Nothing is assigned. In an attempt to write to these bits, write "0". When read the value is indeterminate. However, when SDDS = "1", a "0" value is read. (Note 1)
DL0
__
SDA digital delay set up bit (Note 1, 2, 3, 4, 5)
b7 b6 b5
DL1
DL2
Note 1:
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
: : : : : : : :
Analog 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle
delay is selected of 1/f(X IN) of 1/f(X IN) of 1/f(X IN) of 1/f(X IN) of 1/f(X IN) of 1/f(X IN) of 1/f(X IN)
Digital delay is selected
Note 2:
Note 3: Note 4: Note 5:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3 (U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to; when read, the value is indeterminate. These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate. When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 100ns. Be sure to take this into account when using this device. Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
Fig. 1.104. UART2 special mode register
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.105 shows the functional block diagram for I2C mode. Setting "1" in the I2C mode select bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to "L". The SDA digital delay select bit (bit 7 at address 037716) can be used to select between analog delay and digital delay. When digital delay is selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.42.
P70 through P72 conforming to the simplified I 2C bus
P70/TxD2/SDA
Timer Selector
I/O UART2
D
SDDS = "0" or DL = "000"
To DMA0, DMA1
IICM=0 IICM=1
IICM=1 delay IICM=0
Transmission register
UART2
UART2 transmission/ NACK interrupt request To DMA0
Q T
Noise Filter
Arbitration
IICM=1 IICM=0 Reception register UART2 IICM=0 IICM=1
Timer
UART2 reception/ACK interrupt request DMA1 request
Start condition detection
S
Stop condition detection
Falling edge detection P71/RxD2/SCL I/O
Q
RQ
Bus busy
D T DQ
NACK
Q
L-synchronous output enabling bit
R
Data bus
T
ACK
Selector
(Port P71 output data latch) UART2 IICM=1
9th pulse IICM=1 CLK
Internal clock Bus collision detection
Bus collision/start, stop condition detection interrupt request
Noise Filter Noise Filter
IICM=1
IICM=0
External clock
IICM=0 UART2 IICM=0 UART2
P72/CLK2
Selector
I/O Timer
Port reading * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register.
Fig. 1.105. Functional block diagram for I2C mode
Table 1.42. Delay circuit select conditions
Register value
Contents
IICM SDDS Digital delay is selected DL 001 to 111 000 (000) (000) When digital delay is selected,no analog delay is added. Only digital delay is effective When DL is set ot "000", analog delay is selected no matter what value is set in SDDS. When SDDS is set to "0", DL is initialized, so that DL = "000". When IICM = "0", no delay circuit is selected. Always made sure SDDS = "0".
1
1 1 0
Analog delay is selected
1
No delay
0
0
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An attempt to read Port P71 (SCL) gets the pin's level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the start condition detection, and set to "0" by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception buffer register (037F16), and "1" is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to "1" goes the P71 data register to "0" in synchronization with the SCL terminal level going to "L". Some other functions added are explained here. Figure 1.106 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock.
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mo de register)
0: In normal state
CLK TxD
Enabling transmission With "1: falling edge of RxD2" selected
CLK TxD RxD
Fig. 1.106. Some other functions added
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.107 shows the UART2 special mode register 2. Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table 1.43 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit is set to "1". Figure 1.108 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I2C mode.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR2
Address 037616
When reset 0016
Bit symbol IICM2 CSC SWC ASL STAC SWC2 SDHI SHTC
Bit name I2 C mode selection bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit Refer to Table 1.43 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output
Function
RW
(Note)
0: Enabled 1: Disabled (high impedance) Set this bit to "1" in I 2C mode (refer to Figure 1.108)
Fig. 1.107. UART2 special mode register 2 Table 1.43. Functions changed by I2C mode select bit 2
Function 1 Factor of interrupt number 15 2 Factor of interrupt number 16
IICM2 = 0 No acknowledgment detection (NACK) Acknowledgment detection (ACK)
IICM2 = 1 UART2 transmission (the rising edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) The falling edge of the final bit of the reception clock The falling edge of the final bit of the reception clock
3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK) is assigned to the DMA request factor selection bits 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The rising edge of the final bit of the reception clock
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3 to 6 cycles < duration for setting-up (Note 2) 3 to 6 cycles < duration for holding (Note 2) Note 1 : When the start/stop condition count bit is "1" . Note 2 : "Cycles" is in terms of the input oscillation frequency f(Xin) of the main clock. Duration for setting up
SCL SDA
Duration for holding
(Start condition)
SDA
(Stop condition)
Fig. 1.108. Timing characteristics of detecting the start condition and the stop condition (Note1)
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the instant when the arbitration loss detection flag is set to "1". Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to "0" frees the output fixed to "L". Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows.
(1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn't change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of the clock.
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in I2C Mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to "1" with the serial I/O specified allows the user to output an "1" from the SCL pin even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detection flag is turned on.
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in SPI mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 in SPI mode
The UART2 special mode register 3 (address 037516) is used to activate the SPI mode. Figure 1.109 shows the UART2 special mode register 3.
UART2 Special mode register 3 (I2C and SPI bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR3 Bit symbol SPIM CPHA Bit name
Address 037516
When reset 0016
Function during clock synchronous serial I/O mode SPI mode select bit 0 : Normal mode 1 : SPI mode 0 : Data latched on SPI clock-phase falling clock edge select bit 1 : Data latched on rising clock edge
Function during UART mode
Must always be "0'
RW
Must always be "0'
Nothing is assigned. In an attempt to write to these bits, write "0". When read the __ value is indeterminate. However, when SDDS = "1", a "0" value is read. (Note 1)
DL0
SDA digital delay set up bit (Note 1, 2, 3, 4, 5)
b7 b6 b5
DL1
DL2
Note 1:
000: 001: 010: 011: 100: 101: 110: 111:
Analog delay is selected 2 cycle of 1/f(X IN) 3 cycle of 1/f(X IN) 4 cycle of 1/f(X IN) 5 cycle of 1/f(X IN) 6 cycle of 1/f(X IN) 7 cycle of 1/f(X IN) 8 cycle of 1/f(X IN)
Digital delay is selected
Note 2:
Note 3: Note 4: Note 5:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3 (U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to; when read, the value is indeterminate. These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate. When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 100ns. Be sure to take this into account when using this device. Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
Fig. 1.109. UART2 Special mode register 3
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in SPI mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The SPI functionality is an 8 bit, synchronous communication protocol that is user programmable to use one of four different transfer formats. The four transfer formats support the four combinations of clock phase and clock polarity, as the clock relates to the data. Figure 1.110 shows the SPI system level view. The existing UART2 already provides two of the transfer formats, with the CKPOL control bit. The SPI mode adds the ability to change the phase of the clock, with respect to the transmitted data, in each of the two existing clock polarity formats.
Master MCU MISO MOSI SPICLK SSB Slave MCU MISO MOSI SPICLK SSB
CSB
Slave MCU s SSB input may be tied to ground if there is only one SPI slave in the system.
Fig. 1.110. SPI system level view
When operated in SPI mode the UART2 package pins provide the alternate SPI functions. MOSI, Master Out Slave In, is multiplexed on pin P7[0]/TxD2. MOSI outputs data when UART2 is a SPI master and inputs data when UART2 is a SPI slave. MISO, Master In Slave Out, is multiplexed on pin P7[1]/ RxD2. MISO inputs data when UART2 is a SPI master and outputs data when UART2 is a SPI slave. SPICLK, SPI Clock, is multiplexed on pin P7[2]/CLK2. The SPI clock is input when the SPI is configured as a slave or output when the SPI is configured as a master. SSB, Slave select input, is multiplexed on pin P7[3]/RTSB/CTSB. This pin is used to select the active SPI slave. The M30222 UART2 can be operated as an SPI master or as an SPI slave. Operation as an SPI Slave or SPI Master is determined by the CKDIR contol bit. While in SPI mode, the TxD and RxD pins act as the SPI MOSI and MISO pins. As implemented on the M30222, the SPI pins MOSI and MISO are open drain. There are two added control bits and one added status flag. Control bit SPIM is the SPI Mode enable, which enables SPI operation. CPHA is the Clock Phase selection control bit. CPHA is used to chooses the clock to data relationship. Combined with the existing CKPOL control bit, CPHA provides compatibility with all four SPI transmission modes. CPHA is held at "0" when SPIM = "0". The status flag MDFLT is used to indicate that an SPI mode fault occurred. Several existing configuration bits are required for SPI operation. SPI Slave / Master mode is controlled by the existing CKDIR control bit. The UART is in SPI master mode when the clock is generated internally and is in SPI slave mode when the clock is generated externally. CKPOL control bit select the
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Specifications in this manual are tentative and subject to change
Rev. G UART2 in SPI mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
polarity of the transfer clock. The four different combinations of CKPOL and CPHA define the four formats of the SPI communication protocols. While in SPI mode, the CRD control bit enables the CTS/ RTS pin to operate as SSB and CRS control bit selects CTS/RTS pin to operate as CTS/ SSB. Both contorl bits must be properly configured to activate the SSB function. UFORM control bit selects the UART transfer format, MSB or LSB. SPI data is transmitted MSB first.
SPI operation
Setting SMD[2:0]=010 in U2MR enables either SPI or IIC operation. Operation is undefined if both IICM (U2SMR[0]) and SPI (U2SMR3[0]) control bits are set to logic one while SMD[2:0]=010. Setting the SPIM control bit puts the UART2 into an SPI compatible mode. This mode is only valid in the clock synchronous configuration and must not be entered when the UART2 is configured for asynchronous operation. The internal / external clock select bit (CKDIR) in U2MR) determines whether UART2 is an SPI master or slave. If internal clock is selected, the UART is an SPI master and if external clock is selected, UART2 is an SPI slave. Figure 1.111 shows the signal wave forms. Entering SPI mode has the following effects on operation:
(1) An alternate clock to data relationship can be chosen with the CPHA bit (in U2SMR3). This bit can only be set when SPI bit is a "1". All four SPI clock to data formats are possible by using the CPHA bit together with the CKPOL bit (in U2C0). Figure 1.112 shows the function block diagram of SPI mode. (2) The RxD pin becomes the MISO pin. (3) The TxD pin becomes the MOSI pin. (4) P7[3]/CTSB/RTSB functions as the Slave Select input. This input is active low. (5) When configured as a master, a Mode Fault will be detected if the Slave Select input goes low. If no port pin is assigned to be a slave select input, then mode fault detection is disabled.
SSB
SCLK
CKPOL = 1 CPHA = 1 CKPOL = 1 CPHA = 0 CKPOL = 0 CPHA = 1 CKPOL = 0 CPHA = 0
SCLK
SCLK
SCLK
MISO/MOSI
MSB
LSB
Fig. 1.111. SPI Transmission formats
NOTE: To prevent spurious clock transitions, configure the SPI modules as master or slave before enabling them. Enable the master before enabling the slave. Disable the slave before disabling the master.
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Rev. G UART2 in SPI mode
Specifications in this manual are tentative and subject to change
Fig. 1.112 Functional block diagram of SPI mode
SPI Mode Functional Block Diagram
P70/MOSI Selector
Timer I/O CLKDIR Transmit register Transmit
CLKDIR = 1 = Slave = 0 = Master
SS
Receive Receive register Control
P71/MISO Selector
Timer I/O CLKDIR
1-141
P72/SPICLK Selector Timer I/O Clock Generator CLKDIR CLKDIR Clock Polarity Invert CKPOL Clock Phase Shift CPHA P73/SS Selector Timer I/O CLKDIR Mode Fault Detect UART2 Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M30222 Group
S R
Q
MDFLT
d
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G UART2 in SPI mode Master Mode operation
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SPI Master mode is entered by setting both SPI and CKDIR control bits to logic one. In master mode, the UART will generate the clock to be driven on SPICLK. Transmitted data is shifted out on MOSI and and receive data is shifted in on MISO. The mode fault status flag, MDFLT, is set any time the state of the slave select pin, SS, is inconsistent with an active SPI mode, SPIMSTR or SPISLV. Detection is intended to protect the MCU from damage due to output driver contention. A mode fault occurs if the SS pin of a slave SPI goes high during a transmissionor if the SS pin of a master SPI goes low at any time A Mode Fault causes the following: (1) The CLKDIR bit (in U2MR is forced to a "1". This puts the UART into slave mode so that it is not driving the CLK and MOSI pins. (2) The UART is inhibited from driving it's MISO pin. (3) Mode Fault, MDF, status bit (bit 10 of U2RB) is set. A UART2 receiver interrupt is generated. Mode Fault detection is disabled when the CTS2 /SSB function is not assigned to a port pin. In this case, Slave Select is internally negated if the UART is configured for SPI Master operation. A mode fault is cleared by setting the serial I/O mode bits (bits 2 through 0 of U2MR) to "000". Also, the Receiver Enable bit (RE2 of U2C1) must be cleared. When the Mode Fault is cleared, the UART will return to master mode unless the CRS bit (in U2C0) is explicitly set.
Slave mode operation
SPI Slave mode is entered by setting the SPI control bit to logic one and the CKDIR control bit to logic zero. Before transmission can start, the SSB pin of the slave SPI must be at logic zero. When configured as a SPI slave, UART2 does not initiate any serial transfers. All transfers are initiated by an external SPI bus master. When the CPHA bit is a "1", serial transfers begin with the falling edge of Slave Select. For CPHA = "0", serial transfers begin when the CLK leaves it's idle state (the clock idle state is defined by the CKPOL bit in U2C0). If the UART transmit buffer is empty when a serial transfer starts, the UART will drive the value "80" hexadecimal on it's MISO pin. The SPI should only write to the transmit buffer when it is empty. If the transmit buffer is written during a serial transfer, the new data will be loaded into the transmit shifter at the end of the current transfer. The Slave Select function, SSB, is multiplexed on pin P7[3] along with CTSB. When UART2 is configured for SPI operation, the SSB function must be selected by setting the U2C0 CRD bit to logic "0' to enable CTS/RTS functionality and additionally the U2C0 CRS bit must be set to logic "0" to enable CTS functionality. If the CTS function is not both selected and enabled, the UART2 SPI logic will internally hold the SSB signal to the appropriate level dependant on whether the SPI is configured for master or slave operation. Slave select has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SSB pin is used to select a slave. For CPHA=0, SSB is also used to indicate the start of a transmission. Since it is used to indicate the start of a transmission, SSB must be toggled high and low between each byte transmitted for the CPHA=0 mode For CPHA=1 format, SSB may be kept asserted low between transmitted bytes. If SSB is asserted while the SPI is configured as a master, a Mode Fault occurs.
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Specifications in this manual are tentative and subject to change
Rev. G Serial I/O (3, 4)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O 3, 4
S I/O 3 and S I/O 4 are exclusive clock-synchronous serial I/Os. Figure 1.113 shows the S I/Oi block diagram and Figure 1.114 shows the S I/Oi control register. Table 1.44 shows the specifications of S I/Oi.
SMi1 SMi0
Data bus
f1 f8 f32
Synchronous circuit SMi3 SMi6 S I/O counter i (3)
S I/O i interrupt request
1/2
1/(ni+1)
Transfer rate register
P90/CLK3 (P95/CLK4)
SMi2 SMi3
P92/SOUT3 (P96/SOUT4) P91/SIN3 (P97/SIN4)
SMi5 LSB
MSB
S I/Oi transmission/reception register (8) 8
Note: i = 3, 4.
ni = A value set in the S I/O transfer rate register i (036316, 036716).
Fig. 1.113.
S I/Oi block diagram (i = 3,4)
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O (3, 4)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SiC Bit symbol
SMi0 SMi1 SMi2 SMi3
Address 036216, 036616 Bit name
When reset 4016 Description
b1 b0
RW
Internal synchronous clock select bit
0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Not to be used
SOUTi output disable bit S I/Oi port select bit (Note 2)
0 : SOUTi output 1 : SOUTi output disable (high impedance) 0 : Input-output port 1 : SOUTi output, CLK function
Nothing is assigned. Write "0" when writing to this bit. When read, the value is "0".
SMi5 SMi6 SMi7
Transfer direction select bit Synchronous clock select bit (Note 2) SOUTi initial value set bit
0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock
Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set "1" in bit 2 of the protection register (000A 16) before writing to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to "1", be sure to set the sync clock select bit to "1".
SI/Oi bit rate generator
b7 b0
Symbol S3BRG S4BRG
Address 036316 036716 Indeterminate
When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n + 1
SI/Oi transmit/receive register
b7 b0
Symbol S3TRR S4TRR
Address 036016 036416 Indeterminate
When reset Indeterminate Indeterminate RW
Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input.
Fig. 1.114. S I/O 3, 4 related registers
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Specifications in this manual are tentative and subject to change
Rev. G Serial I/O (3, 4)
Table 1.44. Specifications of S I/O 3, 4
Item Transfer data format Transfer clock * Transfer data length: 8 bits
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications * With the internal clock selected (bit 6 of 036216, 036616 = "1"): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) * With the external clock selected (bit 6 of 036216, 036616 = 0): Input from the CLKi terminal (Note 2) * To start transmission/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216 , 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616)
* If an internal clock is selected, set the bit rate generator divisor (036316, 036716) [It is not necessry to start transmit/receive. It is only needed for operation as intended] -Write transfer data to SI/Oi transmit/receive register (0360 16 , 036416 ) * To use S I/Oi interrupts, the following requirements must be met:
Conditions for transmit/receive start
- Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi transmit/receive register (bit 3 of 004916 , 004816) = 0. Interrupt request generation timing Select function * LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. * Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the SOUTi pin output level during a non-transfer time. For details on how to set, see Figure 1.112. Precaution * Unlike UART0-2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. When the internal clock is selected for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a high-impedance state. However, if the transfer data is written to the SI/Oi transmit/receive register (addresses 036016 , 036416) during this time, SOUTi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. Note 1: ni is a value from 00 16 through FF16 set in the S I/Oi transfer rate register (i = 3, 4). Note 2: With the external clock selected: *Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin input must be in the low state. Also, before rewriting the SI/Oi Control Register (addresses 036216, 036616)'s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held low. * The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it. Therefore, stop the synchronous clock immediately when count reaches eight. If selected, the internal clock stops automatically clocking the SIO channel. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal output, when enabled, stops at the "H" state after transmission is completed. * Rising edge of the last transfer clock. (Note 3)
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r de nt Un pme lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O (3, 4)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions for setting an SOUTi initial value
When using an external clock for the tranfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 1.115 shows the timing chart for setting an SOUTi initial value.
(Example) With "H" selected for SOUTi:
S I/Oi port select bit SMi3 = 0 Signal written to the S I/Oi transmission/reception register SOUTi's initial value set bit (SMi7)
SOUTi initial value select bit SMi7 = 1 "H" level) (SOUTi: Internal
S I/Oi port select bit (SMi3)
S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi)
D0 SOUTi (internal)
SOUTi terminal = "H" output
Port output SOUTi terminal output Initial value = "H" (Note) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi)
D0
Signal written to the S I/Oi register ="L" "H" "L" (Falling edge)
SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register
Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held "H" level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state.
Fig. 1.115. Timing chart for setting SOUTi's initial value
S I/Oi operation timing
Figure 1.116 shows the S I/Oi operation timing.
1.5 cycle (max) SI/Oi internal clock Transfer clock (Note 1) Signal written to the S I/Oi register S I/Oi output SOUTi
(i= 3, 4) "H" "L" "H" "L" "H" "L"
Note 2
"H" "L" "H" "L" Hiz
D0
D1
D2
D3
D4
D5
D6
D7
Hiz
S I/Oi input SINi
(i= 3, 4)
SI/Oi interrupt request bit (i= 3, 4)
"1" "0"
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (i=3,4) (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the S OUTi pin becomes to the high-impedance state after the transfer finishes.
Fig. 1.116. S I/Oi operation timing chart
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD Drive Control Circuit
The M30222 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. * LCD display RAM * Segment output enable register * LCD mode register * Voltage multiplier * Selector * Timing controller * Common driver * Segment driver
*
Bias control circuit
A maximum of 40 segment output pins and 4 common output pins can be used. This allows up to 160 LCD pixels to be controlled. If static drive is enabled, up to 14 of the 40 multiplexed segment pins can be assigned to static drive. The LCD drive control circuit automatically reads the LCD display ram, performs bias and duty ratio control, and displays the data on the LCD panel. The circuit is configured by writing to the LCD mode register, the segment output enable register, the LCD display ram, the LCD frame frequency counter, the LCD expansion register, and the LCD clock divided register. After all these registers are written then the LCD is turned on by setting the LCD enable bit to "1". The LCDRAM output function allows the LCD segment output pins to be used as a general purpose output pin. This mode is configured by writing to the segment output register to enable the segment function, writing a "00" to the time division select bit and "0" to LCD output enable bit, and setting the LCDRAM output enable bit to "1". The data that is written to the LCDRAM bit 4 or 0 will be output on its corresponding segment pin. Note that in this mode VL3 & VL2 must be connected to VDD and VL1 must be connected to VSS. Table 1.45 shows the maximum number of display pixels at each duty ratio. Figure 1.117 shows the block diagram of LCD controller / driver. Figures 1.118 and 1.119 show the LCD-related registers.
Table 1.45. Maximum number of display pixels at each duty ratio
Duty ratio 2 3 4 Maximum number of display pixels (multiplexed) 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits Static drive OFF OFF OFF
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Data bus high-order bits
Rev. G LCD Drive Control Circuit
Data bus low-order bits
LCD enable bit Address 011216 Address 011316 LCD display RAM Duty ratio selection bits LCD frame frequency control counter (8) 2 Voltage multiplier control bit Bias control bit 1/8 Timing controller
Reload register (8) LCDCK count source select bit "0" 1/2 "1"
Address 010016
Address 010116
f32 fC1
Selector Selector Selector Selector LCDCK
Specifications in this manual are tentative and subject to change
Fig. 1.117. Block diagram of LCD controller/driver
Selector Selector Selector Selector
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Level shift Level shift Bias control VCC Level shift Level shift Level Shift Level Shift Level Shift Level Shift LCD output enable bit Segment Segment Segment Segment driver driver driver driver
0 Segment output enable bit 6 0 1 1 Common Common Common Common driver driver driver driver
Level shift
Level shift
Level shift
Level shift
Segment Segment Segment Segment driver driver driver driver
Reload register (8)
1/2
LCD Clock Divider counter (8)
LCD Expansion enable bit
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SEG0
/SYNCout /LCDCLKout
SEG1
SEG2
SEG3
P44/SEG36 P45/SEG37 P46/SEG38 P47/SEG39
VSS VL1 VL2 VL3 C1 C2
COM0 COM1 COM2 COM3
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LCDM
Address 012016
When reset 0X0000002
Bit symbol LCDT0
Bit name
b1 b0
Function
RW
Duty ratio select bit LCDT1 BIAS Bias control bit
0 0 1 1
0: 1: 0: 1:
Not used 2 duty (use COM0, COM1) 3 duty (use COM0 - COM2) 4 duty (use COM0 - COM3)
0 : 1/3 bias 1 : 1/2 bias 0 : LCD Off 1 : LCD On 0 : Voltage multipler disable 1 : Voltage multipler enable (Note 2) 0 : LCD waveform output 1 : LCD data output
LCDEN
LCD enable bit Voltage multiplier control bit
PUMP
LRAMOUT
LCDRAM output bit
Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate.
LSRC LCDCK count source select bit (Note 1) 0 : f32 1 : fc1
__
Note 1: LCDCK is a clock for an LCD timing controller. Note 2: When voltage multiplier is enabled, bias control bit must be "0".
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SEG
Address 012216
When reset 0016
Bit symbol SEG00
Bit name Segment output enable bit 0 Segment output enable bit 1 Segment output enable bit 2 Segment output enable bit 3 Segment output enable bit 4 Segment output enable bit 5 Segment output enable bit 6 LCD output enable
Function 0 : I/O ports P30 to P32 1 : Segment output SEG 24 to SEG26 0 : I/O ports P33 1 : Segment output SEG 27 0 : I/O ports P35 to P34 1 : Segment output SEG 28 to SEG29 0 : I/O ports P37 to P36 1 : Segment output SEG 30 to SEG31 0 : I/O ports P4 0 to P43 1 : Segment output SEG 32 to SEG35 0 : I/O ports P44 to P45 1 : Segment output SEG 36 to SEG37 0 : I/O ports P46 to P47 1 : Segment output SEG 38 to SEG39 0 : Disable 1 : Enable
RW
SEG01 SEG02 SEG03
SEG04
SEG05
SEG06 SEG07
LCD frame frequency counter
b7 b0
Symbol LCDTIM Function
Address 012416
When reset Indeterminate Values that can be set RW
8 bit timer
0016 to FF16
(Note)
X
Note: This register must be changed while LCD output enable bit is "0".
Fig. 1.118. LCD related registers (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD expansion register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LEXP Bit symbol
LEXPEN LCKPOL LSYNC
Address 013016 Bit name
LCD Expansion enable bit
When reset 0016 Function
0 : Disable 1 : Enable 0 : SOF at rising edge 1 : SOF at falling edge 0 : No action 1 : Initiate SYNC
RW
LCD clock out and polarity select bit LCD SYNCout initiation bit
Nothing is assigned. These bits can neither be set nor reset. When read, the value is indeterminate. LSTATCNF0 LSTATCNF1 LSTATEN LCD static drive pin configuration select bits LCD static drive enable bit
0 0 1 1 0 1 0 1 : : : : SEG35 to SEG24 static SEG35 to SEG27 static SEG35 to SEG32 static Do not use
0 : Disable 1 : Enable
LCD clock divide counter
b7 b0
Symbol LCDC Function
Address 013216
When reset Indeterminate Values that can be set RW
8 bit timer
0016 to FF16
X
Fig. 1.119. LCD expansion related register (2)
Voltage Multiplier
The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. (However, when using a 1/2 bias, supply power to the VL1 and VL2 through an external resistor divider.) To activate the voltage multiplier, choose the segment/port and duty rate, select bias control, and set up the LCD frame frequency counter and LCDCK count source using the segment enable register and LCD mode register, then enable the LCD output enable bit (bit 7 at address 012216) and set the voltage multiplier control bit (bit 4 at address 012016) to "1" (= voltage multiplier enabled). When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. The voltage multiplier control bit (bit 4 of the address 012016) controls the voltage multiplier. When using the voltage multiplier, apply a voltage equal to or greater than 1.3 V but not exceeding 2.1 V to the VL1 pin before enabling the voltage multiplier control bit. When not using the voltage multiplier, enable the LCD output enable bit and apply an appropriate voltage to the LCD power supply input pins (VL1 to VL3). When the LCD output enable bit is disabled, the VL3 pin is connected to VCC internally.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bias Control and Applied Voltage to LCD Power Input Pins
To the LCD power input pins (VL1 to VL3), apply the voltage shown in Table 1.46 according to the bias value. Select a bias value by the bias control bit (bit 2 of the address 012016). Figure 1.120 is an example of circuit at each bias.
Table 1.46. Bias control and applied voltage to VL1 to VL3
Bias value 1/3 bias 1/2 bias Voltage value VL3 = VLCD VL2 = 2/3 VLCD VL1 = 1/3 VLCD VL3 - VLCD VL2 = VL1 = 1/2 VLCD
Note: VLCD is the maximum value of supplied voltage for the LCD panel.
Contrast control
Contrast control
VL3
VL3 R1
VL3 R4 VL2
VL3
VL2
VL2
VL2
C2
C2
open R2
C2
open
C2
open
C1
C1
open
C1
open
C1
open
VL1
VL1 R3
VL1 R5
VL1
R1=R2=R3 1/3 bias when using voltage multiplier (VL1<= 2.1V) 1/3 bias when not using voltage multiplier 1/2 bias
R4=R5 When selecting LCDRAM data output (not using LCD panel)
Fig. 1.120. Example of circuit at each bias
Common Pin and Duty Control
The common pins (COM0 to COM3) to be used are determined by the required duty. Table 1.47shows the duty control and the common pins used. Select duty ratio by the duty ratio select bits (bits 0 and 1 of address 012016).
Table 1.47. Duty ratio control and common pins used
Daily ratio select bit Bit 1 2 3 4 0 1 1 Bit 0 1 0 1 COM0, COM1 (Note 1) COM0 to COM2 (Note 2) COM0 to COM3
Duty ratio
Common pins used
Note 1: COM2 and COM3 are open. Note 2: COM 3 is open.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD Display RAM
Address 010016 to 011316 is the designated RAM for the LCD display. When "1's" are written to these addresses, the corresponding segments of the LCD display panel are turned on. Table 1.48 shows the LCD display RAM map.
Table. 1.48. LCD display RAM map
COM
Bit Address
3 7
2 6
1 5
0 4
3 3
21 2 1
0 0 R O O O O O O O O O O O O O O O O O O O O W O O O O O O O O O O O O O O O O O O O O
010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316
SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEF25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG39
SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation. The LCDCK count source frequency is fC1 (same frequency as XCIN) or f32 (divide-by-32 of XIN frequency). Figure 1.121 shows the LCD drive waveform (1/2 bias). Figure 1.122 shows the LCD drive waveform (1/3 bias).
f(LCDCK)= Frame frequency= (frequency of count source for LCDCK) 16 X (LCD frame frequency count value + 1) f(LCDCK) duty ratio
Internal logic LCDCK timing
1/4 duty
Voltage level VL3 VL2=VL1 VSS
COM0 COM1 COM2 COM3 SEG0
VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2=VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Fig. 1.121. LCD drive waveform (1/2 bias)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
1/4 duty Voltage level COM0 VL3 VL2 VL1 VSS
COM1 COM2 COM3 SEG0 VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2 VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Fig. 1.122. LCD drive waveform (1/3 bias)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD Static Drive
When bit 7 of the LCD expansion register is set, then the static drive function is enabled. The following LCD pins get assigned the static drive function in one of the following groups: SEG35 to SEG24, SEG35 to SEG27, or SEG35 to SEG32. Bits 6 and 5 of the LCD expansion register determine the grouping of the static drive pins. All remaining LCD pins retain their normal LCD functions. The waveforms that are output from the static drive pins are shown in Figure 1.123. When writing to LCD RAM for static operation, write the data to all four bits assigned to that pin. (Refer to Table 1.50, LCD display RAM map). For example, to set static SEG34 ON and SEG35 OFF, write F016 to address 011116.
Voltage level
LCDCK
VL3
STATIC COM ["0" written to LCD RAM] STATIC SEG (pixel off) ["0" written to LCD RAM] STATIC SEG (pixel on) ["1" written to LCD RAM]
Vss VL3
Vss VL3
Vss
Fig. 1.123. LCD drive waveform (static drive)
LCD Expansion Clock
When bit 7 of the LCD expansion register is set, the LCD expansion clock becomes active. In this mode a clock (LCDCKout) synchronized to the internal LCD clock can be output from the mcu. The frequency of LCDCLKout is set by the LCD clock divided counter and is: f(LCDCKout) = (frequency of count source for LCDCK) 2 x (LCD clock divided counter + 1) In addition, a synchronization signal (SYNCout) is output. When the LCD SYNCout initiation bit is set, this signal will go active low at the beginning of the next LCD frame. Refer to Figures 1.124 and 1.125.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G LCD Drive Control Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
V32 Xin Osc 1/32 1/2 LCD FFC 1/(n+1)
LCD Frame Freq. LCDCK Duty Ratio 1/8 COM 1/4,1/3,1/2 DQ CLK SEG
XCin
Osc
LCD SYNCout initiation bit
Sync Generator
LCD clock out polarity selection bit
SYNCout
CDC 1/(n+1)
1/2
LCDCKout
DQ CLK
Fig. 1.124. LCD port expansion block diagram
LCDCK Com3 Active
Com2 Active Com1 Active
Com0 Active Initiate Sync
SYNCout 1 Frame Next Frame
Fig. 1.125. LCD port expansion timing diagram
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The VREF connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the lower 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.49 shows the performance of the A-D converter. Figure 1.126 shows the block diagram of the AD converter, and Figures 1.127 and 1.128 show the A-D converter-related registers.
Table 1.49. Performance of A-D converter
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock AD (Note 2) VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of f AD, fAD=f(XIN) VCC = 3V divide-by-2 of f AD/divide-by-4 of fAD, fAD=f(XIN) Resolution Absolute precision 8-bit or 10-bit (selectable) VCC = 5V * Without sample and hold function 3LSB * With sample and hold function (8-bit resolution) 2LSB * With sample and hold function (10-bit resolution) AN0 to AN7 input : 3LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : 7LSB VCC = 3V Operating modes Analog input pins * Without sample and hold function (8-bit resolution) 2LSB to 1MHz
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 8 pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) * Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" * External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ADTRG/P97 input changes from "H" to "L"
A-D conversion start condition
Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the frequency if f(X IN) exceeds 10MHZ, and make AD frequency equal to 10MH Z. Without sample and hold function, set the AD frequency to 250kHZ min. With the sample and hold function, set the AD frequency to 2 MHz min.
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
fAD
1/2
SSH=0
CKS0=1
AD
CKS1=0
1/2
CKS0=0
A-D conversion rate selection
Simultaneous Sample and Hold control
SSH=1
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register A-D control register 1 (address 03D7 16)
A-D control register 0 (address 03D6 16)
Addresses
(03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16)
A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Decoder Vref
Data bus high-order Data bus low-order
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111
OPA1, OPA0
Comparator
OPA1,OPA0=0,0
OPA1,OPA0=1,1 OPA0=1
ANEX0
OPA1,OPA0=0,1
0 0 1 1
0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode
ANEX1
OPA1=1
Fig. 1.126. Block diagram of A-D converter
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0
0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7
b4 b3
is selected is selected is selected is selected is selected is selected is selected is selected
(Note 2)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
b7 b6
BITS CKS1 VCUT OPA0 OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig. 1.127. A-D converter-related registers (1)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
0000XXX02
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Always set to "0"
RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0". SSH Simultaneous sample and hold 0 : Disabled 1 : Enabled
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: SSH must be used ony in conjunction with SMP. Note 3: User must guarantee a conversion of input "1" after a conversion of input "0" in all modes except sweep modes.
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
b0
Address 03C016 to 03CF16
When reset Indeterminate
Function
Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. Write "0" when writing to these bits. When read, the value is "0".
RW
Fig. 1.128. A-D converter-related registers (2)
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.50 shows the specifications of one-shot mode. Figure 1.129 shows the A-D control register in one-shot mode.
Table 1.50. One-shot mode specifications
Item Function Start condition Stop condition Specification The pin selected by the analog input pin select bit is used for one-shot A-D conversion Writing 1 to A-D conversion start flag Writing 0 to A-D conversion start flag End of A-D conversion (A-D conversion start flag changes ot 0 , except when external trigger is selected). End of A-D conversion One of AN0 to AN7 as selected Read A-D register corresponding to selected pin
Interrupt request generation timing Input pin Reading A-D converter results
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 : AN 0 is selected 0 0 1 : AN 1 is selected 0 1 0 : AN 2 is selected 0 1 1 : AN 3 is selected 1 0 0 : AN 4 is selected 1 0 1 : AN 5 is selected 1 1 0 : AN 6 is selected 1 1 1 : AN 7 is selected
b4 b3
(Note 2) (Note 2)
0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0: fAD/4 is selected 1: fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1
Address 03D716 Bit name
When reset 0016 Function
Invalid in one-shot mode
RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit External op-amp connection mode bit
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.129. A-D conversion register in one-shot mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.51 shows the specifications of repeat mode. Figure 1.130 shows the A-D control register in repeat mode.
Table 1.51. Repeat mode specifications
Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading A-D converter results Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing 1 to A-D conversion start flag Writing 0 to A-D conversion start flag None generated One of AN0 to AN7 as selected Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX 2 Function
b2 b1 b0
RW
Analog input pin select bit
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7
b4 b3
is selected is selected is selected is selected is selected is selected is selected is selected
(Note 2) (Note 2)
0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1
Address 03D716 Bit name
When reset 0016 Function
Invalid in repeat mode RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Fig. 1.130. A-D conversion register in repeat mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one AD conversion. Table 1.52 shows the specifications of single sweep mode. Figure 1.131 shows the AD control register in single sweep mode.
Table 1.52. Single sweep mode specifications
Item Function Start condition Stop condition Specification The pin selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Writing 1 to A-D conversion start flag Writing 0 to A-D conversion start flag End of A-D conversion (A-D conversion start flag changes ot 0 , except when external trigger is selected). End of A-D conversion AN0 and AN1 (2 pins), AN0 and AN3 (4 pins), AN0 and AN5 (6 pins), or AN0 and AN1 (8 pins) Read A-D register corresponding to selected pin
Interrupt request generation timing Input pin
Reading A-D converter results
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in single sweep mode
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 0 : Single sweep mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2)
0 0 1 1
0 1 0 1
: AN0, AN1 (2 pins) : AN0 to AN3 (4 pins) : AN0 to AN5 (6 pins) : AN0 to AN7 (8 pins)
MD2 BITS CKS1 VCUT OPA0 OPA1
0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 1 1
0 1 0 1
: : : :
ANEX0 and ANEX1 are not used ANEX0 input is A-D converted ANEX1 input is A-D converted External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: Neither "01" nor "10" can be selected with the external op-amp connection mode bit.
Fig. 1.131. A-D conversion register in single sweep mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.53 shows the specifications of repeat sweep mode 0. Figure 1.132 shows the A-D control register in repeat sweep mode 0.
Table 1.53. Repeat sweep mode 0 specifications
Item Function Start condition Stop condition Interrupt request generation timing Input pin Specification The pin selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Writing 1 to A-D conversion start flag Writing 0 to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 and AN3 (4 pins), AN0 and AN5 (6 pins), or AN0 and AN1 (8 pins) Read A-D register corresponding to selected pin (at any time)
Reading A-D converter results
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 0
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2)
0 0 : AN 0, AN1 (2 pins) 0 1 : AN 0 to AN3 (4 pins) 1 0 : AN 0 to AN5 (6 pins) 1 1 : AN 0 to AN7 (8 pins) 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
MD2 BITS CKS1 VCUT OPA0 OPA1
0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither "01" nor "10" can be selected with the external op-amp connection mode bit.
Fig. 1.132. A-D conversion register in repeat sweep mode 0
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.54 shows the specifications of repeat sweep mode 1. Figure 1.133 shows the A-D control register in repeat sweep mode 1.
Table 1.54. Repeat sweep mode 1 specifications
Item Function Specification All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit. Example: AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc. Writing 1 to A-D conversion start flag Writing 0 to A-D conversion start flag None generated AN0 (1 pin), AN0 and AN1 (2 pins), AN0 and AN2 (3 pins), AN0 and AN3(4 pins) Read A-D register corresponding to selected pin (at any time)
Start condition Stop condition Interrupt request generation timing Input pin Reading A-D converter results
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 1
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 1
0 : Software trigger 1 : AD TRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
A-D sweep pin select bit
When reset 0016 Function
When repeat sweep mode 1 is selected
b1 b0
RW
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2)
0 0 1 1
0 1 0 1
: AN 0 (1 pin) : AN 0, AN1 (2 pins) : AN 0 to AN2 (3 pins) : AN 0 to AN3 (4 pins)
MD2 BITS CKS1 VCUT OPA0 OPA1
1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
b7 b6
0 0 1 1
0 1 0 1
: : : :
ANEX0 and ANEX1 are not used ANEX0 input is A-D converted ANEX1 input is A-D converted External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither `01' nor `10' can be selected with the external op-amp connection mode bit.
Fig. 1.133. A-D conversion register in repeat sweep mode 1
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter (a) Sample and hold
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the speed of conversion increases. As a result, a 28 fAD cycle is achieved with 8bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is converted. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is converted. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "1", input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.134 is an example of how to connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
Analog input
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ANEX0
ANEX1
Comparator External op-amp
Fig. 1.134. Example of external op-amp connection mode
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G A-D Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Operation of Simultaneous Sample and Hold Mode (SSH)
AN1 is sampled exactly the same time as the sampling ofAN0. The actual conversion occurs when a conversion of AN1 is specifically requested. The request can be implicit as a part of a sweep mode or can be explicit by writing an appropriate value to ADCON0. The conversion of input 1 must be completed within 33s after AN0 conversion is started.
A-D Usage Precautions
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 and 7 of A-D control register 2 when A-D conversion is stopped before a trigger occurs.
In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer.
(2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
(5) Use SSH only in conjunction with SMP at 33s.
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MITSUBISHI MICROCOMPUTERS
Rev. G D-A Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = Vref X n/ 256 (n = 0 to 255) Vref : reference voltage
Table 1.55 lists the performance of the D-A converter. Figure 1.135 shows the block diagram of the DA converter. Figure 1.136 shows the D-A control register. Figure 1.137 shows the D-A converter equivalent circuit.
Table 1.55. Performance of D-A converter
Item Conversion Method Resolution Analog output pin R-2R 8 bits 2 channels
Performance
Data bus low-order bits
D-A register0 (8)
(Address 03D816) D-A0 output enable bit
R-2R resistor ladder
P93/DA0
D-A register1 (8)
(Address 03DA16) D-A1 output enable bit
R-2R resistor ladder
P94/DA1
Fig. 1.135. Block diagram of D-A converter
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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
Rev. G D-A Converter
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON Bit symbol
DA0E DA1E
Address 03DC16 Bit name
D-A0 output enable bit D-A1 output enable bit
When reset 0016 Function
0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled
RW
Nothing is assigned. Write "0" when writing to these bits. If read, the value is "0".
D-A register
b7 b0
Symbol DAi (i = 0,1)
Address 03D816, 03DA16
When reset Indeterminate
Function
Output value of D-A conversion
RW
Fig. 1.136. D-A control register
D-A0 output enable bit "0" DA0 "1" 2R MSB D-A0 register0 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: D-A1 is equivalent to this circuit. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register ot 0016 so that no current flows in the resistors Rs and 2Rs.
Fig. 1.137. D-A converter equivalent circuit
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MICROCOMPUTERS
Rev. G CRC Calculation Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.138 shows the block diagram of the CRC circuit. Figure 1.139 shows the CRC-related registers. Figure 1.140 shows the calculation example using the CRC calculation circuit
Data bus high-order bits Data bus low-order bits
Eight low-order bits CRC data register (16)
Eight high-order bits (Addresses 03BD 16, 03BC 16)
CRC code generating circuit x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE 16)
Fig. 1.138. Block diagram of CRC circuit
CRC data register
(b15) b7 (b8) b0 b7 b0
Symbol CRCD
Address 03BD16, 03BC16
When reset Indeterminate Values that can be set
000016 to FFFF16
Function
CRC calculation result output register
RW
CRC input register
b7 b0
Symbo CRCIN Function
Data input register
Address 03BE16
When reset Indeterminate Values that can be set
0016 to FF16
RW
Fig. 1.139. CRC-related registers
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MITSUBISHI MICROCOMPUTERS
Rev. G CRC Calculation Circuit
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b15
b0
(1) Setting 000016
CRC data register CRCD [03BD16, 03BC16]
b7
b0
(2) Setting 0116
CRC input register
CRCIN [03BE16]
2 cycles After CRC calculation is complete
b15 b0
118916
CRC data register
CRCD [03BD16, 03BC16]
Stores CRC code The code resulting from sending 01 16 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 9 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
(3) Setting 2316
CRC input register
CRCIN [03BE16]
After CRC calculation is complete
b15 b0
0A4116
CRC data register
CRCD [03BD16, 03BC16]
Stores CRC code
Fig. 1.140. Calculation example using the CRC calculation circuit
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MITSUBISHI MICROCOMPUTERS
Rev. G I/O Ports
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 55 programmable I/O ports: P3 to P10 (excluding P5, P83 and P87). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P83 is an input-only port and has no built-in pull-up resistance. P70 and P71 do not have pull up resistors. Figures 1.141 to 1.143 show the programmable I/O ports. Figure 1.144 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.145 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.146 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.147 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input.
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MITSUBISHI MICROCOMPUTERS
Rev. G I/O Ports
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P3, P4
Direction register
VL3/VCC VL2/VCC VL3/VCC "1" "1" LCD drive timing
Interface logic level shift circuit Data bus Port latch Segment output Port/segment DQ Timer A overflow CK Port ON/OFF VL2/VSS
P62, P66, P77, P82, P86, P91, P97
Pull-up selection Direction register
Data bus
Port latch
P60, P61, P63, P64, P65, P67, P72, P73, P74, P75, P76, P77, P80, P81, P82, P90, P92-4
Pull-up selection
Direction register "1"
Output Data bus Port latch
Input respective peripheral functions
Fig. 1.141. Programmable I/O ports (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P70 to P71
Direction register "1"
Output Data bus Port latch
Input respective peripheral functions
P83
Data bus
NMI interrupt input
P100 to P105
Pull-up selection Direction register
Data bus
Port latch
Analog input
P95, P96, P106, P107
Direction register
Pull-up selection
"1"
Output Data bus Port latch (Note)
Input to respective peripheral functions
Analog input Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port.
Fig. 1.142. Programmable I/O ports (2)
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MITSUBISHI MICROCOMPUTERS
Rev. G I/O Ports
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P93 , P94
Pull-up selection D-A output enabled Direction register
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog output
D-A output enabled
Note :
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin.
COM0 TO COM3, SEG0 TO SEG23
VL3
VL2 VL1
The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value.
VSS
Fig. 1.143. Programmable I/O ports (3)
CNVSS CNVSS signal input (Note)
RESET RESET signal input (Note)
Note :
symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin.
Fig. 1.144. I/O pins
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Rev. G I/O Ports
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi (i = 3 to 10, except 5 and 8)
Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 03E716, 03EA16, 03EE16, 03EF16, 03F316, 03F616
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 3, 4, 6, 7, 9, 10)
When reset 0016
RW
Bit name
Port Pi 0 direction register Port Pi 1 direction register Port Pi 2 direction register Port Pi 3 direction register Port Pi 4 direction register Port Pi 5 direction register Port Pi 6 direction register Port Pi 7 direction register
16
Note: Set bit 2 of protect register (address 000A the port P9 direction register .
to "1" before rewriting to
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD8
Bit symbol
PD8_0 PD8_1 PD8_2
Address 03F216
Bit name
Port P8 0 direction register Port P8 1 direction register Port P8 2 direction register
When reset 00X000002
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
RW
Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate. PD8_4 PD8_5 PD8_6 Port P8 4 direction register Port P8 6 direction register Port P8 7 direction register
__
Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate.
Fig. 1.145. Direction register
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi (i = 3 to 10, except 5 and 8)
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Address 03E516, 03E816, 03EC16, 03ED16, 03F116, 03F416
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (Note) (i = 3, 4, 6, 7, 9, 10)
When reset Indeterminate
RW
Bit name
Port Pi 0 register Port Pi 1 register Port Pi 2 register Port Pi 3 register Port Pi 4 register Port Pi 5 register Port Pi 6 register Port Pi 7 register
Note: Because P7 and P71 are n-channel open drain ports, the data are high impedance.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8
Bit symbol
P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6
Address 03F016
Bit name
Port P8 0 register Port P8 1 register Port P8 2 register Port P8 3 register Port P8 4 register Port P8 5 register Port P8 6 register
When reset X000000016
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit except for P83) 0 : "L" level data 1 : "H" level data
RW
Nothing is assigned. Write "0" when writing to this bit. When read, the value is indeterminate.
Fig. 1.146. Port register
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M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
XXXX XX
Symbol PUR0 Bit symbol
Address 03FC16 Bit name
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Nothing is assigned. Write "0" when writing to these bits
PU06 PU07 P30 to P33 pull-up P34 to P37 pull-up
OO OO OO
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
PU10 PU11
Address 03FD16 Bit name
P40 to P43 pull-up P44 to P47 pull-up
When reset 0016 (Note 1) Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW
Nothing is assigned. Write "0" when writing to these bits.
OO
PU14 PU15 PU16 PU17
P60 to P63 pull-up P64 to P67 pull-up P7 2, P73 pull-up (Note 2) P74 to P77 pull-up
Note 1: When the V CC level is being impressed to the CNV SS terminal, this register becomes to 0216 when reset (PU11 becomes to "1"). Note 2: Because P70 and P71 are n-channel open-drain ports, the pull up is not available.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2 Bit symbol
PU20 PU21 PU22 PU23 PU24 PU25
Address 03FE16 Bit name
P80 to P82 pull-up P84 to P86 pull-up (Except P83) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Nothing is assigned. Write "0" when writing to these bits. When read, the value is indeterminate.
Fig. 1.147. Pull-up register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Unused Pins
Table 1.56. Example of connections for unused pins
Pin Name Ports P3 to P10 (excluding P5, P83, P87) Xout (Note) NMI AVcc AVss, VREF C1, C2 VL2, VL3 VL1 CNVss COM0 to COM3 SEG0 to SEG23
Connection After setting for input mode, enable internal pull-up resistors or connect every pin to Vss cia a resistor. Or, after setitng for output mode, leave these pins open. Open Connect to Vcc via pull-up resistor Connect Vcc Connect to Vss Open Connect to Vcc Connect to Vss Connect to Vss via pull-up resistor Open Open
Note: With external clock input to Xin pin.
Microcomputer
Port P3 to P10 (except for P5, P83) (Input mode) * * * (Input mode)
(Output mode)
* * *
Open
Open Open Open
Xcout COM0 to COM3 SEG0 to SEG23
NMI XOUT AVCC VL3 VL2 VL1 AVSS VREF Open VCC
CNVss C1, C2
Open VSS
Fig. 1.148. Example of connections for unused pins
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Rev. G Electrical Characteristics
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.57. Absolute maximum ratings
Symbol Vcc AVcc VI Supply voltage Analog supply voltage Input voltage RESET, , P30 to P37, P40 to P47, P60 to P67, P72 to P77, P80 to P86, P90 to P97, P100 to P107, Vref, Xin, CNVss (mask ROM version) VL1 VL2 VL3 P70, P71, C1, C2, CNVss (flash memory version) VO Output voltage P60 to P67, P72 to P77, P80 to P82, P84 to P86, P90 to P97, Xout, P30 to P37, P40 to P47 When output port When segment output P70, P71, CNVss (mask ROM version) Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature Ta=25oC Parameter Condition Vcc=AVcc Vcc=AVcc Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to Vcc + 0.3 Unit V V V
-0.3 to VL2 VL1 to VL3 VL2 to 6.5 -0.3 to 6.5
V V V V
-0.3 to Vcc + 0.3
V
-0.3 to Vcc -0.3 to VL3 -0.3 to 6.5
V V V
300 -40 to 85 -65 to 150
mW
oC o
C
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MITSUBISHI MICROCOMPUTERS
Rev. G Electrical Characteristics
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.58. Recommended operating conditions (referrenced to Vcc = 2.7 to 5.5V at Ta = -20 to 85C or 40 to 85C (Note 3) unless othewise specified)
Standard Symbol Parameter Min Vcc AVcc Vss Avss VIH Supply voltage Analog supply voltage Supply voltage Analog supply voltage High Input voltage Xin, RESET, CNVss, BYTE, P31 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P86, P90 to P97, P100 to P107 P70, P71 0.8 Vcc 0.8 Vcc 0 2.7 Typ. 5.0 Vcc 0 0 Vcc Max 5.5 V V V V V Unit
6.5
V
VIL
Low input voltage High peak output current (Note 2) High average output current (Note 1) Low peak output current (Note 2) Low average output current (Note 1)
Xin, RESET, CNVss, P30 to P37, P40 to P47, P60 to P67,P70 to P77, P80 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P72 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P72 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P72 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P72 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 Vcc=TBD to 5.5V No wait Vcc=2.7V to TBD
0.2 Vcc
V
IOH (peak) IOH (avg) IOL (peak) IOL (avg)
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
0 0 0 0 32.768
16 TBD 16 TBD 50
MHz MHz MHz MHz KHz
f(Xin)
Main clock input oscillation frequency (Note 3) Subclock oscillation frequency
Vcc=TBD to 5.5V With Wait Vcc=2.7V to TBD
f(Xcin)
Note 1: The average output current is the mean value within 100ms. Note 2: The total IOL (peak) and IOH (peak) fo ports P3, P4, P6, P7, P80 to P82, P84 to P86, P9 and P10 must be 80 mA max. Note 3: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency (Mask ROM version, Flash memory 5V version, no wait) Main clock input oscillation frequency (Mask ROM version, Flash memory 5V version, with wait)
Operating maximum frequency [MHZ]
Operating maximum frequency [MHZ]
16.0
TBD
16.0
TBD
TBD
TBD
0.0 2.7 TBD
Supply voltage[V]
0.0 2.7 TBD
Supply voltage[V]
5.5
5.5
(BCLK: no division)
(BCLK: no division)
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MITSUBISHI MICROCOMPUTERS
Rev. G Electrical Characteristics
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.59. Electrical characteristics (referenced to Vcc = 5V, Vss = 0V at Ta = 25C, f(Xin) = 16MHz unless otherwise specified.
Standard Symbol Parameter Measuring condition Min VOH High output voltage High output voltage High output voltage High output voltage VOL Low output voltage Low output voltage Low output voltage Low output voltage VT + - VTHysteresis P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 Xout High power Low power Xcout High power Low power P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 Xout High power Low power Xcout High power Low power TA0in to TA4in, TA0in to TB3in, INT0 to INT5, ADTRG, CTS0, CTS1, CLK0, CLK1, TA2out to TA4out, NMI, KI0 to KI4 RESET Xin, RESET, CNVss, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P86, P90 to P97, P100 to P107 Xin, RESET, CNVss, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P86, P90 to P97, P100 to P107 P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P82, P84 to P86, P90 to P97, P100 to P107 Xin Xcin When clock is stopped 2.0 VI=5V IOH=-5mA 3.0 Typ. Max V Unit
VOH
IOH=-200A
4.7
V
VOH
IOH=-1mA IOH=-0.5mA With no load applied With no load applied IOL=-5mA
3.0 3.0 3.0 1.6 2.0
V V V V V
VOL
IOL=-200A
0.45
V
VOL
IOL=-1mA IOL=-0.5mA With no load applied With no load applied 0.2 0 0
2.0 2.0
V V V V
0.8
V
VT + - VTIIH
Hysteresis High input current
0.2
1.8 5.0
V A
IIL
Low input current
VI=0
-5.0
A
RPULLUP
Pull-up resistance
VI=0V
30.0
50.0
167.0
k
R R
f(Xin) f(Xcin)
Feedback resistance Feedback resistence RAM retention voltage
1.0 6.0
M M V
VRAM
Mask ROM versions
f(Xin) =16 MHz Square wave, no division f(Xin) =16 MHz Square wave, no division f(Xcin) =32 kHz Square wave f(Xcin) =32 kHz Square wave f(Xcin) =32 kHz When a WAIT instruction is executed
30.0
50.0
mA
Flash memory 5V version
35.0
50.0
mA
Mask ROM versions
90.0
A
Icc
Power supply current
Flash memory 5V version
8.0
mA A
4.0
o Ta =25 C when clock is stopped o Ta = 85 C when clock is stopped
1.0 A 20.0
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MITSUBISHI MICROCOMPUTERS
Rev. G Electrical Characteristics
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.60. A-D conversion characterisitics (referenced to Vcc = AVcc + Vref = 5V, Vss = AVss = 0V at Ta = 25C, f(Xin) = 16MHz unless otherwise specified)
Standard Symbol Parameter Measuring Condition Min. _ _ Resolution Absolute Accuracy Sample & Hold function not available Sample & Hold function available (10 bit) Vref = Vcc Vref = Vcc = 5V Typ. Max. 10 +/-3 Bits LSB Unit
Vref = Vcc = 5V
AN0 to AN7 input ANEX0, ANEX1 input, external op-amp connection mode
+/-3 +/-7
LSB LSB
Sample & Hold function available (8 bit) RLADDER tCONV tCONV tSAMP Vref VIA Ladder resistence Conversion time (10 bit) Converstion time (8 bit) Sampling time Reference voltage Analog input voltage
Vref = Vcc = 5V
+/-2
LSB
Vref = Vcc
10 3.3 2.8 0.3 2 0
40
k s s s
Vcc Vref
V V
Table 1.61. D-A conversion characteristics (referenced to Vcc = 5V, Vss = AVss = 0V, Vref = 5V at Ta = 25C, f(Xin) = 16MHz unless otherwise specified)
Standard Unit Min. Typ. Max. 8 1.0 3 4 (Note) 10 20 1.5 Bits % s k m
Symbol
Parameter
Measuring Condition
_ _ tSU RO IVref
Resolution Absolute Accuracy Settling time Output resistance Reference power supply input current
Note: This applies when using one D-A converter, with the D-A register. The unused D-A converter is set to 00 16 . The A-D converter s ladder resistance is not included. When the Vref is disconnected at the A-D control register, IVref is sent.
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MITSUBISHI MICROCOMPUTERS
Rev. G Electrical Characteristics
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (referenced to Vcc = 5V, Vss = 0V at Ta = 25 C unless otherwise stated) Table 1.62 External clock input
Standard Symbol Parameter Min. tC tW(H) tW(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time 62.5 25 25 15 15 Max. ns ns ns ns ns Unit
Table 1.63. Timer A input (counter input in event counter mode)
Standard Symbol Parameter Min. tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 40 40 Max. ns ns ns Unit
Table 1.64. Timer A input (gating input in timer mode)
Standard Symbol Parameter Min. tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width 400 200 200 Max. ns ns ns Unit
Table 1.65. Timer A input (external trigger input in one-shot timer mode)
Standard Symbol Parameter Min. tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width 200 100 100 Max. ns ns ns Unit
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MITSUBISHI MICROCOMPUTERS
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M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.66. Timer A input (external trigger input in pulse width modulation mode)
Standard Symbol Parameter Min. tW(TAH) tW(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 Max. ns ns Unit
Table 1.67. Timer A input (up/down input in event counter mode)
Standard Symbol Parameter Min. tC(UP) tW(UPH) tW(UPL) tSU(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit
Table 1.68. Timer B input (counter input in event counter mode)
Standard Symbol Parameter Min. tC(TB) tW(TBH) tW(TBL) tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) 100 40 40 200 80 80 Max. ns ns ns ns ns ns Unit
Table 1.69. Timer B input (pulse period measurement mode)
Standard Symbol Parameter Min. tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width 400 200 200 Max. ns ns ns Unit
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MITSUBISHI MICROCOMPUTERS
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M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (referenced to Vcc = 5V, Vss = 0V at Ta = 25 C unless otherwise stated) Table 1.70. Timer B input (pulse width measurement mode)
Standard Symbol Parameter Min. tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width 400 200 200 Max. ns ns ns Unit
Table 1.71. A-D trigger input
Standard Symbol Parameter Min. tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width 400 200 200 Max. ns ns ns Unit
Table 1.72 Serial I/O
Standard Symbol Parameter Min. tC(CK) tW(CKH) tW(CKL) td(C-Q) th(D-C) tSU(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time 0 30 90 200 100 100 80 Max. ns ns ns ns ns ns ns Unit
Table 1.73. External interrupt INTi inputs
Standard Symbol Parameter Min. tW(INH) tW(INL) INTi input HIGH pulse width INTi input LOW pulse width 250 250 Max. ns ns Unit
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MITSUBISHI MICROCOMPUTERS
Rev. G Description (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
The M30222 (flash memory version) has an internal new DINOR (Divided bit line NOR) flash memory that can be rewritten with a single power source. Three flash memory modes are available that read, program, and erase: parallel I/O and standard serial I/O modes that flash memory manipulates using a programmer, and a CPU rewrite mode that flash memory can manipulate using the Central Processing Unit (CPU). Each mode is detailed in the following pages. The flash memory is divided into several block as shown in Figure 1.149 so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the users application system. This boot ROM area can be rewritten in only parallel I/O mode.
Outline Performance
Table 1.74 shows the outline performance of the M30222 (flash memory version).
Table 1.74. Outline performance
Item Erase/Write voltage Flash memory operation mode Erase block division User ROM area Boot ROM area Program method Erase method Program/erase control method Number of Commands Program/erase count ROM code protect 2.7 to 5.5V
Performance
Three modes: CPU rewrite, parallel I/O, standard serial See Fig. 1.149 One division (8 Kbytes) (Note) uses word units Collective erase/block erase Program/erase control by software command 8 100 Parallel I/O and standard serial modes are supported.
Note: The boot area contains a standard serial I/O control mode control program stored in it when it is shipped from the factory. This area can be erassed and programmed in paralell I/O mode only.
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M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7D00016 Block 8 : 4 Kbytes 7E000 16 Boot ROM area: 8 Kbytes 7FFFF 16 80000 16 BFFFF 16 C000016 D000016 Block 6 : 64 Kbytes E0000 16 Block 5 : 64 Kbytes F0000 16 Block 4 : 32 Kbytes F8000 16 Block 3 : 24 Kbytes FE000 16 Block 2: 4 K byte FF000 16 Block 1: 4 K byte FFFFF 16
Reserved
Block 7 : 64 Kbytes
User ROM area: Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited. Note 2: To specify a block, use the maximum address in the block that is an even address.
Figure 1.149. Block diagram of flash memory version
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). Only the user ROM area shown in Figure 1.149 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to RAM memory before it can be executed.
Microcomputer Mode and Boot Mode
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVss pin low. In this case, the CPU starts executing the control program in the user ROM area. When the microcomputer is reset and both the CNVss pin and P74 (CE) pin are pulled high, the CPU starts operating using the control program in the boot ROM area (program start address is C000016, 7D00016). This mode is called the "boot" mode. The control program for CPU rewrite mode must be written into the user ROM or boot ROM area beforehand. (If the control program is written into the boot ROM area, standard serial I/O mode becomes unusable.) See Figure 1.149 for details about the boot ROM area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command.
Outline Performance
In the CPU rewrite mode, the CPU erases, programs, and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it can be executed. The CPU rewrite mode is accessed by writing "1" for the CPU rewrite mode select bit (bit 1 in address 034B416). Software commands are accepted once the mode is accessed. In the CPU rewrite mode, software commands are used to write and read data into even-numbered addresses ("0" for byte address A0) in 16-bit units. Always write 8-bit software comands into evennumbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 1.150 shows the flash memory control register.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMCR Bit symbol
Address
03B416
When reset
XXXX00012
Bit name RY/BY status flag
Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Normal mode 1: CPU rewrite mode 0: Normal operation 1: Reset 0: Write protected 1: Write enabled
RW
FMCR0
FMCR1
CPU rewrite mode select bit (Note 1)
FMCR2 FMCR3 FMCR4
CPU rewrite mode entry flag
Flash memory reset bit (Note 2)
O OO OO
Write protect Bit (Note 1)
Nothing is assigned. When write, set "0". When read, values are indeterminate. Note 1: For this bit to be set to 1, the user needs to write a "0" and then a "1" to it in succession. Use the control program in RAM for write to this bit. Note 2: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession when the CPU rewrite mode selection bit is = "1".
Fig. 1.150 Flash memory control registers
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1". Bit 1 is the CPU rewrite mode select bit. When this bit is set to "1", the M30222 accesses the CPU rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, the control program that sets this bit must be executed out of RAM. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. The bit can be set to "0" by only writing a "0". Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to "0". If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Figure 1.151 shows a flowchart for setting/releasing the CPU rewrite mode. Bit 4 is the flash memory protect bit. The blocks are write protected when this bit is "0". The write protect is disabled when the bit is "1". The MCU must be in CPU rewrite mode for this bit to have any effect. To set this bit to "1", it is necessary to write "0" and then write "1" in succession.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program in ROM
Program in RAM
*1
Start
Single-chip mode or boot mode (Note 1)
Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession) (Note 3)
Set processor mode register (Note 2)
Check CPU rewrite mode entry flag
Transfer CPU rewrite mode control program to internal RAM
Using software command execute erase, program, or other operation
Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM)
Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 4)
*1 Write "0" to CPU rewrite mode select bit
End
Note 1: Apply 5V +/- 10% to CNVss pin by confirmation of CPU rewrite mode entry flag when starting operation with single-chip mode. Note 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716: 5 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state); 10 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state) Note 3: For CPU rewrite mode sleect bit to be set to "1", the user needs to write a "0" and then a"1" to it in succession. When not in this mode, it is not in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 4: Before exiting the CPU, rewrite mode after completing erase or program operation, always be sure to execute a read array command to reset the flash memory.
Figure 1.151. CPU rewrite mode set/reset flowchart
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation speed During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 5.0 MHz or less when wait bit (bit 7 at address 000516) = 0 (no wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (one wait state) (2) Instruction inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction. JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be used by transferring the vector into the RAM area. (4) Reset If the MCU is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Set a 5 ms wait to release the reset operation. Also, when the reset has been released, the program execute start address is automatically set to 07E00016, therefore program so that the execute start address of the boot ROM is 07E00016.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.75. List of software commands (CPU rewrite mode)
1st Bus Cycle Commands (Note 1) Cycle No. Mode Write Write Write Write Write Write Write Write Write Write Address X (Note 5) X X X X X X X X X Data (D7:D0) FFh 90h 70h 50h 40h 20h 20h A7h 71h 77h Write Write Write Write Read Write WA (Note 3) BA (Note 4) X X BA (Note 4) BA (Note 4) WD (Note 3) D0h 20h D0h (D6)(Note 6) D0h Read Read IA X ID SRD (Note 2) Mode 2nd Bus Cycle Address Data (D7:D0)
Read ID Codes Status Regiser Read Status Register Clear Word Program Auto Block Erase Erase (Erase all unlocked blocks) Lock Bit Status Read Lock Bit Program
1 2 2 1 2 2 2 2 2 2
Note Note Note Note Note Note
1: 2: 3: 4: 5: 6:
When a software command is input, the high-order byte of data (D15:D8) is ignored. SRD = Status Register Data WA = Write Address, WD = Write Data (16 bits) BA = Block Address (Enter the maximum address of each block that is an even address) X denotes a given even address in the user ROM. Lock bit output on Data bit 6
Software Commands
Table 1.75 lists the software commands available with the M30222 (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Read Array Command (FF16)
The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0 -D15), 16 bits at a time. The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code "7016" is written in the first bus cycle, the content of the status register is read out at the data bus (D0-D7) by a read in the second bus cycle. The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the error bits of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version) Program Command (4016)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the second bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by reading the status register or the RY/BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0-D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written. The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Figure 1.152 shows an example of a program flowchart.
Start
Write 401 6
Write address and data
Read status register
SR7=1? or RY/BY=1
NO
YES NO Program error
SR4= 0 YES Program complete
Fig. 1.152. Program flowchart
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Command (2016/2016) (Erases all blocks regardless of lock status)
By writing the command code "2016" in the first bus cycle and the confirmation command code "2016" in the second bus cycle that follows, the system starts erase all blocks (erase and erase verify). Whether the erase all blocks command is terminated can be confirmed by reading the status register or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the erase operation starts and is returned to "1" upon completion. The read status register mode remains active until the read array command (FF16) is written. The Boot Block area is not affected by this command. The RY/BY status flag is "0" during erase operation and "1" when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed.
Block Erase Command (2016/D016)
By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed by reading the status register or the RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the clock erase operation starts and is returned to "1" upon completion of the block erase operation. In this case, the read status register mode remains active until the Read Array command (FF16). The RY/BY status flag is "0" during block erase operation and "1" when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Start
2 016 : All blocks A 716 : Only unlocked blocks
Write 2016/A716
Write 2016/D016
Block address
2 016 : Chip erase A 716 : Block/Chip erase
Read status register
SR7=1? or RY/BY=1
NO
YES NO Erase error
SR5= 0 YES Erase completed
Fig. 1.153. Erase flowchart
Erase All Unlocked Blocks Command (A716/D016)
By writing the command code "A716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows, the system starts erase all unlocked blocks (erase and erase verify). Whether the erase all unlocked blocks command is terminated can be confirmed by reading the status register or the RY/BY status flag. When the erase all unlocked blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the erase operation starts and is returned to "1" upon completion of the erase operation. The read status register mode remains active until the Read Array command (FF16) is written. The RY/BY status flag is "0" during erase operation and "1" when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Figure 1.153 shows an example of a block erase flowchart.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Start
Write 771 6
Write 771 6 Block address
RY/BY Status Flag =1?
NO
YES NO Lock bit program error
SR4= 0? YES Lock bit program completed
Fig. 1.154. Lock Bit Program Flowchart
Lock Bit Program Command (7716/D016)
This command is available only when the lock bit is enabled. For CPU rewrite mode bit 4 must be a "1". In parallel mode WPB must be a "0". By writing the command code ("7716") in the first bus cycle and the confirmation code ("D016") and block address in the second cycle the lock bit can be programmed for the block specified. The lock bit protects the block against erase during the erase all unlocked blocks command. The status of the lock bit can be read by issuing the Lock bit status read command. Figure 1.154 is an example of a lockbit program flowchart.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Start
Write 711 6
Enter Block address
(Note) D6 = 0?
NO
Blocks not locked
YES Blocks locked Note: Data Bus bit 6
Fig. 1.155. Lockbit Status Read Flowchart
Lock Bit Status Read Command (7116)
This command is available only when the lock bit is enabled. For CPU rewrite mode bit 4 must be a "1". In parallel mode WPB must be a "0". By writing the command code ("7116") in the first bus cycle and reading the Block address and data bit 6 in the second cycle, the value of the lock bit for that block address can be read. A "0" means that the block is locked. A "1" means that the block is unlocked. Figure 1.155 is an example of a lockbit status read flowchart.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Protect Function (Block Lock)
Each block in Figure 1.156 has a nonvolatile lock bit to specify that the block be protected (locked) against erase or write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of against each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0's lock bit disable bit is used.
(1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. On the other hand, the blocks where the lock bit data =1 are not locked, they're enabled for erase/write. (2) When the lock bit disable bit =1, all blocks are unlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data, that is 0 (locked), is set to 1 (unlocked) after erase, so that the lock bit lock is removed.
7D000 16 Block 8 : 4 Kbytes 7E000 16
Block 7 : 64 Kbytes
BFFFF 16 C0000 16 D0000 16
Block 6 : 64 Kbytes E0000 16 Block 5 : 64 Kbytes F0000 16 Block 4 : 32 Kbytes F8000 16 Block 3 : 24 Kbytes
Flash Flash memory memory size start address 260 Kbytes 7D000 16 C0000 16
FE000 16 Block 2: 4 K byte FF000 16 Block 1: 4 K byte FFFFF 16
Fig. 1.156. Block diagram of user area
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register
The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways.
(1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16). Also, the status register can be cleared by writing the clear status register command (5016). After a reset, the status register is set to "8016". Table 1.76. Definition of each bit in status register
Definition Each SRD bit Status name 1 SR7 (bit 7) SR6 (bit 6) SR5 (bit 5) SR4 (bit 4) SR3 (bit 3) SR2 (bit 2) SR1 (bit 1) SR0 (bit 0) Write state machine (WSM) status Reserved Erase status Program status Reserved Over write back status Over erase status Reserved Ready _ Terminated in error Terminated in error _ Terminated in error Terminated in error _ 0 Busy _ Terminated normally Terminated normally _ Terminated normally Terminated normally _
Each bit in this register is explained below. Sequencer status (SR7)
After power-on, the sequencer status is set to 1 (ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared.
Program status (SR4)
The program status informs the operating status of write operation to CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (2016) is not the confirmation command (D016), both the program status and erase status (SR5) are set to 1. When the program status or erase status = 1, the following commands entered by the command write are not accepted. Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or erase all unlocked blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first busy cycle is cancelled.
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version) Over Write Back Status (SR2)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The over write back status informs the operating status of the write back operation during an erase sequence. When a write back error occurs, SR5 and SR2 are set to "1". The over write back status is reset to "0" when cleared.
Over Erase Status (SR1)
The over erase status informs the operating status of the erase operation during an erase sequence. When an erase error occurs, SR5 and SR1 are set to "1". The over erase status is reset to "0" when cleared. If SR5 or SR4 bits = "1", the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Bits SR2 and SR1 give more information on the reason for failure. Also, if any commands are not correct, both SR5 and SR4 are set to 1.
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.157 shows a full status check flowchart and the action to be taken when each error occurs.
Read status register
SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES
YES
Command sequence error
Execute the clear status register command (50 16) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
NO
Block erase error
NO
Program error (page or lock bit)
If an error occurs, the block in error cannot be used.
End (block erase, program)
Note: When one of SR5 to SR4 is set to 1, none of the page program, block erase, or erase all blocks commands is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 1.157 Full status check flowchart and remedial procedure for errors
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions to Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect register
The ROM code protect function prevents reading out or modifying the contents of the flash memory during parallel I/O mode. Figure 1.158 shows the ROM code protect control address (0FFFFF16). It is located at the hightest 8 bits of the 32 bit reset vector. If one of the pair of ROM code protect bits is set to "0", ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to "00", ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is tuned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ROMCP
Address 0FFFFF16
When reset FF16
Bit symbol
Bit name
Function
Always set this bit to "1"
b3 b2
Reserved bit
ROMCP2
ROM code protect level 2 set bit (Note 1, 2)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
b5 b4
ROMCR
ROM code protect reset bit (Note 3)
00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective
b7 b6
ROMCP1
ROM code protect level 1 set bit (Note 1)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LST tester, etc., is also inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, because these bits cannot be changed in paralell input/ output mode, they need to be rewritten in one of the two other modes.
Fig. 1.158. ROM code protect control addrsss
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MITSUBISHI MICROCOMPUTERS
Rev. G CPU Rewrite Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match: If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Figure 1.159 shows the storage location for the code addresses.
Address 0FFFDF16 to 0FFFDC16 0FFFE316 to 0FFFE016 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE8 16 0FFFEF16 to 0FFFEC16 0FFFF316 to 0FFFF016 0FFFF716 to 0FFFF416 0FFFFB16 to 0FFFF816 0FFFFC16 to 0FFFFF16 ID3 ID4 ID5 ID6 ID7 ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector
ROMCP Reset
4 bytes
Fig. 1.159. Code address storage
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MITSUBISHI MICROCOMPUTERS
Rev. G Parallel I/O Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. Figure 1.160 shows the pin layout for flash paralell mode. Table 1.77 is adescription of pin functions in paralell I/O mode. Use an exclusive programmer supporting M30222 (flash memory version). Refer to the instruction manual of each programmer make for the detail of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.149 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.149. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 07E00016 through 07FFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.
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MITSUBISHI MICROCOMPUTERS
Rev. G Parallel I/O Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P97/ADtrg/LED7/Sin4/INT3
Mode set-up method Signal Value CNVss Reset SCLK Vcc Vss Vss
P106/AN6/INT6
P107/AN7/INT7
Vss
COM2 COM0 COM1 VL2 VL1 VL3 C2 C1
P103/AN3
P100/AN0
P102/AN2
P104/AN4
P105/AN5
P101/AN1
AVcc 99
AVss
Vref
Vcc
100
92
98
97
96
95
94
93
91
90
89
88
87
86
85
84
83
82
81
COM3 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 SEG14 Vss SEG15 Vcc VDC SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P30 SEG25/P31 D15
0.1 F Capacitor
P96/ANEX1/Sout4 P95/ANEX0/CLK4 P94/DA1/TB4in A15 A14 A13 A12 P93/DA0/TB3in P92/TB2in/Sout3 P91/TB1in/Sin3 P90/TB0in/INT2/CLK3 P86/INT1 CNVss A11 A10 Reset CNVss P85/Xcin P84/Xcout RESET Xout Vss Xin Vcc A9 A8 A7 A6 RP
EXT PULSE
IWP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
80 79 78
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
77 76 75 74 73 72 71 70 69 68 67 66 65
M30222FG
P83/NMI P82/INT0 P81/TA4IN/INT5/U P80/TA4OUT/INT5/U P77/TA3IN/INT4 P76/TA3OUT/INT4 P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TxD2/SDA/TA0OUT P67/TxD1/KI7 P66/RxD1/KI6
17 18 19 20 21 22 23
64 63 62 61 60 59 58
A16 A17 A18 A19 A0 A1 A2 A3 A4 A5
WE CE OE BSEL BYTE RY/BY OSC
Fig. 1.160. Pin Connections for Flash Parallel Mode
24 25 26 27 28 29 30 43 45 42 44 33 34 35 36 37 38 40 46 47 48 49 31 P65/CLK1/KI5 41 50 39 32 P64/CTS1/RTS1/CTS0/CLKS1/KI4 P60/CTS0/RTS0/KI0 P63/TxD0/KI3 P61/CLK0/KI1 SEG39/P47/RTP1 SEG38/P46/RTP0 SEG37/P45 SEG36/P44 SEG35/P43 SEG33/P41 SEG31/P37 SEG30/P36 SEG29/P35 P62/RxD0/KI2 SEG34/P42 SEG32/P40 SEG28/P34 SEG27/P33 SEG26/P32
57 56 55 54 53 52 51
1-203
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MITSUBISHI MICROCOMPUTERS
Rev. G Parallel I/O Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.77. Description of pin function in parallel I/O mode
Pin Name Vcc, Vss CNVss RESET Xin/Xout AVcc, AVss P30 P31 P32 to P37 P40 to P47 P60 P61 P62 to P65 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85
Signal name Power input CNVss Reset input Clock input Analog power supply Address Bit 4 Address Bit 5 Input port P3 Input port P4 Input port P6 SCLK Input port P6 OSC RY/BY BYTE BSEL input OE input CE input WE input EXTPULSE RP Address Bit 6 Address Bit 7 Address Bit 8 Address Bit 9 Address Bit 10 Address Bit 11
I/O I I I I I I I
Function Apply 2.7-5.5 V to Vcc pin and O V to Vss pin Connect 0.1 f capacitor from Vcc to Vss Connect to Vss No connection required for parallel flash programming Connect AVss to Vss and AVcc to Vcc Address Bit 4 Address Bit 5 No connection required for parallel flash programming No connection required for parallel flash programming No connection required for parallel flash programming
I
Connect to Vss No connection required for parallel flash programming
O O I I I I I I I I I I I I I
Flash oscillator Ready / Busy signal Byte mode control mode Boot select mode Output enable pin Chip enable pin Write enable pin External pulse for test modes Deep power down pin Address Bit 6 Address Bit 7 Address Bit 8 Address Bit 9 Address Bit 10 Address Bit 11
1-204
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MITSUBISHI MICROCOMPUTERS
Rev. G Parallel I/O Mode (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Name P90 P91 P92 P94 to P95 P97 Vref P100 to P107 VL1 to VL3 C1 to C2
COM0 to COM2
Signal name Address Bit 12 Address Bit 13 Address Bit 14 Input port 9 Input port 9 A/D Vref voltage Input port P10 LCD power supply LCD condenser COM ports IWP Data Bits 0 - 15 Address Bit 16 Address Bit 17 Address Bit 18 Address Bit 19 Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3
I/O I I I Address Bit 12 Address Bit 13 Address Bit 14
Function
No connection required for parallel flash programming No connection required for parallel flash programming I Connect A/D reference voltage to Vcc Input H , L or leave open I Connect VL1 to Vss; VL2 and VL3 to Vcc Leave open Leave open I I/O I I I I I I I I Write protect pin Data Bits 0 - 15 Address Bit 16 Address Bit 17 Address Bit 18 Address Bit 19 Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3
COM3
SEG0 to SEG15
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
1-205
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program erase, etc.) the internal flash memory. There are two standard serial I/O modes that require a purpose specific peripheral unit. * Serial I/O Mode 1 is synchronized * Serial I/O Mode 2 is as asynchronized The standard serial I/O mode is different from the parallel I/O mode because it uses the CPU rewrite mode to control flash memory rewrite, rewrite data input and so on. It is started when the reset is released. This is done when the P50 (CE) pins is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. In an ordinary command mode, the CNVss pin is set to "L" level. This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Please note that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in parallel I/O mode. In standard serial I/O mode, only the user ROM area (see Figure 1.181) can be rewritten. The boot ROM cannot. Also, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit are not accepted unless the ID code matches. Figure 1.161 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 and mode 2 according to the level of CLK1 pin when the reset is released.
Serial I/O Mode 1
To use standard serial I/O mode 1, set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). the CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. the RTS1 (BUSY) pin outputs an "L" level when ready for reception and "H" level when reception starts.
Serial I/O Mode 2
To use standard serial I/O mode 2, set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1.
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 1 (clock synchronous)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programmer, etc.) using 4-wire clock-synchronous serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P56 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units LSB first. When busy, such as during transmission, reception, erasing or program execution the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level. Also, data and status register in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register.
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P97/ADtrg/LED7/Sin4/INT3
P106/AN6/INT6
P107/AN7/INT7
Vss
COM2 COM0 COM1 VL2 VL1 VL3 C2 C1
P100/AN0
P103/AN3
P102/AN2
P104/AN4
P105/AN5
P101/AN1
Mode set-up method Signal Value CNVss Vcc Vss Vcc Reset
AVcc 99
AVss
Vref
Vcc
100
92
98
97
96
95
94
93
91
90
89
88
87
86
85
84
83
82
81
80 79 78
P96/ANEX1/Sout4 P95/ANEX0/CLK4 P94/DA1/TB4in P93/DA0/TB3in P92/TB2in/Sout3 P91/TB1in/Sin3 P90/TB0in/INT2/CLK3 P86/INT1
COM3 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 SEG14 Vss SEG15 Vcc VDC SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P30 SEG25/P31
0.1 F Capacitor
1
2 3 4 5 6 7 8
77 76 75 74 73 72 71 70 69
CNVss
CNVss P85/Xcin P84/Xcout
9 10 11 12
Reset
RESET Xout Vss Xin Vcc P83/NMI P82/INT0 P81/TA4IN/INT5/U P80/TA4OUT/INT5/U P77/TA3IN/INT4 P76/TA3OUT/INT4 P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TxD2/SDA/TA0OUT P67/TxD1/KI7 P66/RxD1/KI6
Fig. 1.161. Pin connections for Flash Serial I/O mode
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 35 31 P65/CLK1/KI5 32 P64/CTS1/RTS1/CTS0/CLKS1/KI4 P63/TxD0/KI3 TXD P61/CLK0/KI1 SCLK P62/RxD0/KI2 RXD
68 67 66 65
M30222FG
64 63 62 61 60 59 58 57 56 55 54 53 52 51
36 P60/CTS0/RTS0/KI0 BUSY
37 SEG39/P47/RTP1
1-208
38 SEG38/P46/RTP0
40 SEG36/P44
46
43
45
42
44
41
50
48
49
47
39 SEG37/P45
SEG35/P43
SEG33/P41
SEG31/P37
SEG30/P36
SEG29/P35
SEG34/P42
SEG32/P40
SEG28/P34
SEG27/P33
SEG26/P32
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
Table 1.78. Pin connections for serial I/O mode
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Name Vcc, Vss CNVss RESET Xin/Xout
Signal name Power input CNVss Reset input Clock input
I/O I/O I I I
Function Apply 2.7 to 5.5 V to Vcc pin and 0 V to the Vss pin Connect to Vcc Connect Vss Connect a ceramic resonator or crystal oscillator between Xin and Xout pins. To input an externally generated clock, input it to Xin and open Xout pin Connect AVss to Vss and AVcc to Vcc Input H , L , or leave open Input H , L , or leave open Standard serial mode 1: Busy signal output pin Standard serial mode 2: Monitors program operation check. Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input L Serial data input pin Serial data output pin Input H , L , or leave open Input H , L , or leave open Input H , L , or leave open Input H , L , or leave open Input H , L , or leave open Input A/D reference voltage Connect VL1 to Vss; VL2 and VL3 to Vcc when LCD is not used Connect a condenser between C1 and C2 when using LCD voltage multiplier. Leave open when not used. Leave open 0.1F capacitor connect to Vss
AVcc, AVss P30 to P37 P40 to P47 P60 P61 P62 P63 P64 to P67 P70 to P77 P80 to P86 P90 to P97 P100 to P107 Vref VL1 to VL3 C1 to C2
COM0 to COM3
Analog power supply Input port P3 Input port P4 Busy SCLK RxD input TxD output Input port P6 Input port P7 Input port P8 Input port P9 Input port P10 A/D Vref voltage LCD power supply LCD condenser COM ports Voltage Down Converter
I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O
VDC
1-209
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.79 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Software commands are explained here below.
Table 1.79. Software commands (Standard serial I/O mode 1)
Control command 1 Page read FF16 4116 2016 A716 7016 5016 7116 Address (middle) Address (middle) Address (high) Address (high) Lock bit data output D016 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output SRD output 3rd byte Address (high) Address (high) Address (high) 4th byte Data output Data input 5th byte Data output Data input 6th byte Data output Data input Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable
2
Page program
3
Block erase
D016
4
Erase all unlocked blocks Read status register Clear status register Read lock bit status Lock bit program Lock bit enable
5
6
Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable Address (low) Size (low) Version data output Address (middle) CRC data (Low) Address (low) Address (low) Address (middle) Size (high) Version data output Address (high) CRC data (High) Address (middle) Address (middle) Address (high) Address (high) Address (high) Check sum ID size ID1 ID7 Acceptable
7
8
7716
9
7A16 7516 F516 FA16
10
Lock bit disable
11
ID check function Download function Version data output function
12
Data input Version data output Data output
As required Version data output Data output Version data output to 9th byte Data output to 259th byte
Not acceptable Acceptable
13
FB16
Version data output
14
Boot ROM area output function Read check data
FC16
Data output
Not acceptable Not acceptable
15
FD16
16
Word Read
FE16 4016 B916
Not acceptable Not acceptable Acceptable
17
Word Program
18
Exit
Note 1: The shaded areas indicate a transfer from flash MCU to serial programmer. All other data is transferred from programmer to MCU. Note 2: SRD to Status Register Data. SRD1 refers to Status Register 1 Data. Note 3: All commands are accepted if the reset vector is blank.
1-210
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (1) Page Read Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with address A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
RxD0
FF16
A8 to A15
A16 to A23
TxD0
data0
data255
RTS0(BUSY)
Fig. 1.162. Timing for page read
(2) Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
CLK0
RxD0
4116
A8 to A15
A16 to A23
data0
data255
TxD0
RTS0(BUSY)
Fig. 1.163. Timing for the page program
1-211
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (3) Block Erase Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command erases the data in the specified block. Execute the block erase command as explained here following: (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address the specified block for addresses A8 to A23. When block erasing ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.
CLK0
RxD0
2016
A8 to A15
A16 to A23
D016
TxD0
RTS0(BUSY)
Fig. 1.164. Timing for block erase
(4) Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command explained below. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erase ends, the RTS0 (BUSY) signal changes from "H" to "L". The result of the erase operation can be known by reading the status register. Each block can be erase protected with the lock bit. For more information, see the Data Protection Function section.
CLK1
RxD1 (M16C receive data) TxD1 (M16C transmit data) RTS1(BUSY)
A716
D016
Fig.1.165. Timing for erasing all unlocked blocks
1-212
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (5) Read Status Register Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
CLK0
RxD0
7016
TxD0
SRD output
SRD1 output
RTS0(BUSY)
Fig. 1.166. Timing for reading the status register
(6) Clear Status Register Command
This command clears the bits (SR4 - SR5) which are set when the status register operation register operation ends in error. When the "5016" command code is sent with thefirst byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS0 (Busy) signal changes from the "H" to the "L" level.
CLK0
RxD0
5016
TxD0
RTS0(BUSY)
Fig. 1.167. Timing for clearing the status register
1-213
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (7) Read Lock Bit Status Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads the lock bit status of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of the specified block for address A8 to A23.
CLK0
RxD0 (M16C receive data) TxD0 (M16C transmit data) RTS0(BUSY)
7116
A8 to A15
A16 to A23
D016
Fig. 1.168. Timing for reading lock bit status
(8) Lock Bit Program Command
This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for address A8 to A23. When writing ends, RTS0 (BUSY) signal changes from the "H" to "L". Lock bit status can be read with the read lock bit status command. For information on the lock bit function an reset procedure, see the Data Protection Function section.
CLK1
RxD1 (M16C receive data) TxD1 (M16C transmit data) RTS1(BUSY)
7716
A8 to A15
A16 to A23
D016
Fig. 1.169. Timing for the lock bit program
1-214
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (9) Lock Bit Enable Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; It does not set the lock bit itself.
CLK0
RxD0 (M16C receive data) TxD0 (M16C transmit data) RTS0(BUSY)
Fig. 1.170. Timing for enabling the lock bit
7A16
(10) Lock Bit Disable Command
This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; It does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled.
CLK0
RxD0 (M16C receive data) TxD0 (M16C transmit data) RTS0(BUSY)
Fig. 1.171. Timing for disabling the lock bit
7516
1-215
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (11) ID Check
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0
F516
DF16
FF16
0F16
ID size
ID1
ID7
TxD0
RTS0(BUSY)
Fig. 1.172. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFEF16, 0FFFF316, 0FFF716, and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDF16 to 0FFFDC16 0FFFE316 to 0FFFE016 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE816 0FFFEF16 to 0FFFEC16 0FFFF316 to 0FFFF016 0FFFF716 to 0FFFF416 0FFFFB16 to 0FFFF816 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset
4 bytes
Fig. 1.173. ID code storage addresses
1-216
r d e ent U n opm l ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (12) Download Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal RAM.
CLK0
RxD0
FA 16
Data size (low)
Check sum
Program data
Program data
TxD0
Data size (high)
RTS0(BUSY)
Fig. 1.174. Timing for download
(13) Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
CLK0
RxD0
FB16
TxD0
'V'
'E'
'R'
'X'
RTS0(BUSY)
Fig. 1.175. Timing for version information output
1-217
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (14) Boot ROM Area Output Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK0
RxD0
FC16
A8 to A15
A16 to A23
TxD0
data0
data255
RTS0(BUSY)
Fig. 1.176. Timing for boot ROM area ouput
(15) Read CRC Data
This command reads the CRC data that confirms that the write data sent with the page program command was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The CRC data (low) is received with the 2nd byte and the CRC data (high) with the 3rd byte. To use this command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After the read CRC command is executed again, the CRC data for all the read data that was sent with the page program command is read. The CRC data is the result of CRC operation of write data.
CLK1
RxD1
(M16C receive data)
FD 16
TxD1
(M16C transmit data)
CRC data (low) CRC data (high)
RTS1(BUSY)
Fig. 1.177. Timimg for the read CRC data
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (16) Word Read Program
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads the word from the specific address. To execute the word read command: (1) Transfer the "FE16" command code with the 1st byte. (2) Transfer the 3 byte address starting with the A0-A8 with the next 3 bytes. (3) The MCU transfers the byte at the specific address. (4) The MCU transfers the byte at the specific address +1. Note: The specified address may be odd or even (A0=0 or 1) and be any value withing the 1M address space.
CLK0
RxD0
FE16
Address Low
Address Middle
Address High
TxD0
1st half of word
2nd half of word
RTS0(BUSY)
Fig. 1.178. Timimg for the word read program
(17) Word Program
This command writes the word in the flash memory. To execute the word program command: (1) Transfer the "4016" with the 1st byte. (2) Transfer the 3 byte address starting with the A0-A8 with the next 3 bytes. (3) Transfer the 1st half of the word to be written in the lower address (A0=0). (4) Transfer the 2nd half of the word to be written in the higher address (A0=1). Note: The specified address must be even (A0=0).
CLK0
RxD0
4016
Address Low
Address Middle
Address High
1st half of word
2nd half of word
TxD0
RTS0(BUSY)
Figure 1.179. Timing for the word program
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) (18) Exit Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command does a software reset by writing a "1" to bit 3 of the Processor Mode register 0. To execute the Exit command: (1) Transfer "B916" with the 1st byte. (2) Transfer the confirm command code "D016" in the 2nd byte. If the CNVss line is low, the MCU will reset in normal mode and begin execution of the user code. If CNVss is high, the MCU will reset back into boot mode and begin execution at 7E00016 again.
CLK1
RxD1
B916
D016
TxD1
RTS1(BUSY)
Figure 1.180.. Timing for the exit command
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version) Data Protection (Block Lock)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Each of the blocks in Figure 1.181 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable enable is determined by the status of the lock bit itself and executing status of the lock bit disable and lock bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked and cannot e erased or written in. On the other hand, blocks with a "1" lock bit data are unlocked and can be erased or written in. (2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was "0" before the block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the lock bit.
7D000 16 Block 8 : 4 Kbytes 7E000 16
Block 7 : 64 Kbytes
BFFFF 16 C0000 16 D0000 16
Block 6 : 64 Kbytes E0000 16 Block 5 : 64 Kbytes F0000 16 Block 4 : 32 Kbytes F8000 16 Block 3 : 24 Kbytes
Flash Flash memory memory size start address 260 Kbytes
7D00016 C000016
FE000 16 Block 2: 4 K byte FF000 16 Block 1: 4 K byte
User ROM area
FFFFF 16
Fig. 1.181. Block in the user area
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.80 gives the definition of each status register bit. After clearing the reset, the status register outputs "8016".
Table 1.80. Status register (SRD)
Definition Each SRD bit Status name 1 SR7 (bit 7) SR6 (bit 6) SR5 (bit 5) SR4 (bit 4) SR3 (bit 3) SR2 (bit 2) SR1 (bit 1) SR0 (bit 0) Write state machine (WSM) status Reserved Erase status Program status Reserved Reserved Reserved Reserved Ready _ Terminated in error Terminated in error _ _ _ _ 0 Busy _ Terminated normally Terminated normally _ _ _ _
Sequencer status (SR7)
After power-on, the sequencer status is set to 1 (ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations.
Erase Status (SR5)
The erase status reports the operating status of the automatic erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0".
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0".
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks, and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.81 gives the definition of each status register 1 bit. "0016" is output when power is turned ON and the flag status is mainteined even after the reset.
Table 1.81. Status register definitions for SRD1
Definition SRD 1 bits Status Name 1 SR15 (bit 7) SR14 (bit 6) SR13 (bit 5) SR12 (bit 4) SR11 (bit 3) SR10 (bit 2) SR9 (bit 1) SR8 (bit 0) Data receive time out Reserved Boot update complete bit Reserved Reserved Checksum match bit ID check completed bits Match 0 0 1 1 Time out _ 0 1 0 1 Update completed _ _ No match Not verified Verification mismatch Reserved Verified Normal operation _ 0 Not completed _ _
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downlaoded to the RAM or not, using the download function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program is downloaded for execution using the download function.
ID Check completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure 1.182 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES
YES
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
NO
Block erase error
NO Program error
Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used.
End (block erase program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the
Fig. 1.182. Full status check flowchart and remedial procedure for errors
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 1 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for the Standard Serial I/O Modes 1 and 2
Figure 1.183 shows a circuit application for the standard serial I/O modes 1 and 2. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information.
Clock input BUSY output Data input Data output
CLK0 RTS0(BUSY) RXD0 TXD0
M16C/ M30222 Flash memory version
CNVss CNVss NMI
RESET
Reset
(1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual.
Fig. 1.183. Example circuit application for serial I/O modes 1 and 2
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0). Standard serial I/O mode 2 is engaged by releasing the reset with the P61 (CLK0) pin "L" level. The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.183) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.83). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully (see Note). Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. Note: If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock.
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Peripheral Unit
MCU with internal flash memory
(1) Transfer "B016"
"B016"
Reset
If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU outputs "B016". If other than 10 or 16 MHz, the MCU does not output anything.
(2) Transfer "0016" 16 times
1st
"B016" "0016" "0016" "0016" "0016" "B016"
At least 15ms transfer interval
2nd
15th 16th
(3) Transfer check code "B016"
The bit rate generator setting completes (9600 bps)
Figure 1.83. Peripheral unit and initial communication
Identifying frequency
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.182 gives the operation frequency and the baud rate that can be attained for. Table 1.82. Operation frequency and baud rate
Operation frequency (MHz) 16 12 11 10 8 7.3728 6 5 4.5 4.194304 4 3.58 3 2 + : Communications possible - : Communications not possible Baud rate 9600 bps + + + + + + + + + + + + + + Baud rate 19200 bps + + + + + + + + + + + + + Baud rate 38400 bps + + + + + + + + Baud rate 57600 bps + + + + -
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version)
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.183 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.183. Software commands (Standard serial I/O mode Page Read Command
Control command 1 Page read FF16 4116 2016 A716 7016 5016 7116 Address (middle) Address (middle) Address (high) Address (high) Lock bit data output D016 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output SRD output 3rd byte Address (high) Address (high) Address (high) 4th byte Data output Data input 5th byte Data output Data input 6th byte Data output Data input Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable
2
Page program
3
Block erase
D016
4
Erase all unlocked blocks Read status register Clear status register Read lock bit status Lock bit program Lock bit enable
5
6
Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable Address (low) Size (low) Version data output Address (middle) CRC data (Low) Address (low) Address (low) Address (middle) Size (high) Version data output Address (high) CRC data (High) Address (middle) Address (middle) Address (high) Address (high) Address (high) Check sum ID size ID1 ID7 Acceptable
7
8
7716
9
7A16 7516 F516 FA16
10
Lock bit disable
11
ID check function Download function Version data output function
12
Data input Version data output Data output
As required Version data output Data output Version data output to 9th byte Data output to 259th byte
Not acceptable Acceptable
13
FB16
Version data output
14
Boot ROM area output function Read CRC data
FC16
Data output
Not acceptable Not acceptable
15
FD16
16
Word Read
FE16 4016 B916 B016 B116
Not acceptable Not acceptable Acceptable
17
Word Program
18 19 20
Exit Baud rate 9600 Baud rate 19200 Baud rate 38400 Baud rate 57600
B016 B116
Acceptable Acceptable
21
B216 B316
B216 B316
Acceptable
22
Acceptable
Note 1: The shaded areas indicate a transfer from flash MCU to serial programmer. All other data is transferred from programmer to MCU. Note 2: SRD to Status Register Data. SRD1 refers to Status Register 1 Data. Note 3: All commands are accepted if the reset vector is blank.
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (1) Page Read Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
RxD1
(M16C receive data)
FF16
A8 to A15
A16 to A23
TxD1
(M16C transmit data)
data0
data255
Figure 1.184. Timing for page read
(2) Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When the reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the page program is known by reading the status register. Each block can be write protected with the lock bit. Additional writing is not allowed with the pages programmed already.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
4116
A8 to A15
A16 to A23
data0
data255
Figure 1.185. Timing for the page program
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (3) Block Erase Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command erases the data in the specified block. To execute the block erase command : (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A16 to A23. When block erase ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. Afterward, the result of the block erase operation is known by reading the status register. Each block can be erase-protected with the lock bit.
RxD1
(M16C receive data)
2016
A8 to A15
A16 to A23
D016
TxD1
(M16C transmit data)
Figure 1.188. Timing for block erase
(4) Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the erase operation is known be reading the status register. Each block can be erase protected with the lock bit.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
Figure 1.187. Timing for erasing all unlocked blocks
A716
D016
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (5) Read Status Register Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
RxD1
(M16C receive data)
7016
TxD1
(M16C transmit data)
Figure 1.188. Timing for reading the status register
SRD output
SRD1 output
(6) Clear Status Register Command
This command clears the bits (SR3-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, bits SR3-SR5 are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
Figure 1.189. Timing for clearing the status register
5016
(7) Read Lock Bit Status Command
This command reads the lock bit status of the specified block. To execute the lock bit status command: (1) Transfer the "7116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of the specified block for address A8 to A23.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
Figure 1.190. Timing for lock bit status
7116
A8 to A15
A16 to A23
D016
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (8) Lock Bit Program Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command writes "0" (lock) for the lock bit of the specified block. To execute the lock bit program command : (1) Transfer the "7716" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is written for the lock bit of the specified block. Write the highest address of the specified block for address A8 to A23. When writing ends, RTS1 (BUSY) signal changes from the "H" to "L". Lock bit status can be read with the read lock bit status command.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
7716
A8 to A15
A16 to A23
D016
Figure 1.191. Timing for the lock bit program
(9) Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code "7A16" is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; It does not set the lock bit itself.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
Figure 1.192. Timing for enabling the lock bit
7A16
(10) Lock Bit Disable Command
This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; It does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, "0" (locked) lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
Figure 1.193. Timing for disabling the lock bit
7516
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (11) ID Check
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command checks the ID code. To execute the boot ID check command: (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 1.194. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDF16 to 0FFFDC16 0FFFE316 to 0FFFE016 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE816 0FFFEF16 to 0FFFEC16 0FFFF316 to 0FFFF016 0FFFF716 to 0FFFF416 0FFFFB16 to 0FFFF816 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset
4 bytes
Figure 1.195. ID code storage addresses
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (12) Download Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command downloads a program to the RAM for execution. To execute the download command: (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
FA 16
Data size (low)
Check sum
Program data
Program data
Data size (high)
Figure 1.196. Timing for download
(13) Version Information Output Command
This command outputs the version information of the control program stored in the boot area. To execute the version information output command: (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
FB16
'V'
'E'
'R'
'X'
Figure 1.197. Timing for version information output
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MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (14) Boot ROM Area Output Command
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). To execute the boot ROM area output command: (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
RxD1 (M16C receive data) TxD1 (M16C transmit data)
FC16
A8 to A15
A16 to A23
data0
data255
Figure 1.198. Timing for Boot ROM area output
(15) Read CRC Data
This command reads the CRC data that confirms that the write data sent with the page program command was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The CRC data (low) is received with the 2nd byte and the CRC data (high) with the 3rd byte. To use this command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After the read CRC command is executed again, the CRC data for all the read data that was sent with the page program command is read. The CRC data is the result of CRC operation of write data.
RxD1
(M16C receive data)
16 FD
TxD1
(M16C transmit data)
CRC data (low) CRC data (high)
Figure 1.199. Timing for the read CRC data
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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (16) Word Read Program
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command reads the word from the specific address. To execute the word read command: (1) Transfer the "FE16" command code with the 1st byte. (2) Transfer the 3 byte address starting with the A0-A8 with the next 3 bytes. (3) The MCU transfers the byte at the specific address. (4) The MCU transfers the byte at the specific address +1. Note: The specified address may be odd or even (A0=0 or 1) and be any value withing the 1M address space.
RxD0
FE16
Address Low
Address Middle
Address High
TxD0
Figure 1.200. Timing for Word read program
1st half of word
2nd half of word
(17) Word Program
This command writes the word in the flash memory. To execute the word program command: (1) Transfer the "4016" with the 1st byte. (2) Transfer the 3 byte address starting with the A0-A8 with the next 3 bytes. (3) Transfer the 1st half of the word to be written in the lower address (A0=0). (4) Transfer the 2nd half of the word to be written in the higher address (A0=1). Note: The specified address must be even (A0=0).
RxD0
4016
Address Low
Address Middle
Address High
1st half of word
2nd half of word
TxD0
Figure 1.201. Timing for Word program
(18) Exit Command
This command does a software reset by writing a "1" to bit 3 of the Processor Mode register 0. To execute the Exit command: (1) Transfer "B916" with the 1st byte. (2) Transfer the confirm command code "D016" in the 2nd byte. If the CNVss line is low, the MCU will reset in normal mode and begin execution of the user code. If CNVss is high, the MCU will reset back into boot mode and begin execution at 7E00016 again.
RxD1
B916
D016
TxD1
Figure 1.202. Timing for Exit command
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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (19) Baud Rate 9600
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command changes baud rate to 9,600 bps. To execute: (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD1
(M16C receive data)
B016
TxD1
(M16C transmit data)
B016
Figure 1.203. Timing of baud rate 9600
(20) Baud Rate 19200
This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD1
(M16C receive data)
B116
TxD1
(M16C transmit data)
B116
Figure 1.204. Timing of baud rate 19200
(21) Baud Rate 38400
This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD1
(M16C receive data)
B216
TxD1
(M16C transmit data)
B216
Figure 1.205. Timing of baud rate 38400
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r de n t Un p m e lo ve de Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
Rev. G Serial I/O Mode 2 (Flash Memory Version) (22) Baud Rate 57600
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD1
(M16C receive data)
B316
TxD1
(M16C transmit data)
B316
Figure 1.206. Timing of baud rate 57600
Example Circuit Application for the Standard Serial I/O Modes 1 and 2
Figure 1.207 shows a circuit application for the standard serial I/O modes 1 and 2. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information.
Clock input BUSY output Data input Data output
CLK0 RTS0(BUSY) RXD0 TXD0
M16C/ M30222 Flash memory version
CNVss CNVss NMI
RESET
Reset
(1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual.
Fig. 1.207. Example circuit application for serial I/O modes 1 and 2
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